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ST93C47CM6013TR Datasheet(PDF) 5 Page - STMicroelectronics |
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ST93C47CM6013TR Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 13 page Figure 5. Synchronous Timing, Read or Write AI00820C C D Q ADDRESS INPUT Hi-Z tDVCH tCLSL A0 S DATA OUTPUT tCHQV tCHDX tCHQL An tSLSH tSLQZ Q15/Q7 Q0 AI01429 C D Q ADDRESS/DATA INPUT Hi-Z tDVCH tSLCH A0/D0 S WRITE CYCLE tSLSH tCHDX An tCLSL tSLQZ BUSY tSHQV tW READY counter automatically rolls over to ’00’ when the highest address is reached. Programming is internally self-timed (the external clock signal on C input may be disconnected or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruc- tion. The Write instruction writes 8 or 16 bits at one time into one of the 128 bytes or 64 words. After the start of the programming cycle a Busy/Ready signal is available on the Data output (Q) when Chip Select (S) is High. An internal feature of the ST93C46 provides Power-on Data Protection by inhibiting any opera- tion when the Supply is too low. The design of the ST93C46 and the High Endurance CMOS technol- ogy used for its fabrication give an Erase/Write cycle Endurance of 1,000,000 cycles and a data retention of 40 years. The DU (Don’t Use) pin does not affect the function of the memory and it is reserved for use by SGS- THOMSON during test sequences.The pin may be left unconnected or may be connected to VCC or VSS. Direct connection of DU to VSS is recom- mended for the lowest standby power consump- tion. DESCRIPTION (cont’d) 5/13 ST93C46A/46C/46T, ST93C47C/47T |
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