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STA015B Datasheet(PDF) 10 Page - STMicroelectronics |
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STA015B Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 44 page SCLK_POL=0 SCLK_POL=4 DATA IGNORED DATA VALID SCKR SCKR SDI BIT_EN D98AU968A DATA IGNORED Figure 9. Serial Input Interface Clocks DATA SOURCE µP MPEG DECODER IIC D98AU912 IIC SDO SCKT LRCKT SERIAL AUDIO INTERFACE SDI SCKR BIT_EN XTO DAC RX TX XTI FILT PLL OCLK SCL SDA DATA_REQ Figure 8. MPEG Decoder Interfaces. 2.2 - Serial Input Interface STA015 receives the input data (MSB first) thought the Serial Input Interface (Fig.5). It is a serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Se- rial Clock). The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock. The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. For proper operation Bit_EN line should be toggled only when SCRK is stable low (for both SCLK_POL configuration) The possible configurations are described in Fig. 9. 2.3 - PLL & Clock Generator System When STA015 receives the input clock, as de- scribed in Section 2.1, and a valid layer III input bitstream, the internal PLL locks, providing to the DSP Core the master clock (DCLK), and to the Audio Output Interface the nominal frequencies of the incoming compressed bit stream. The STA015 PLL block diagram is describedin Figure 5. The audio sample rates are obtained dividing the oversampling clock (OCLK) by software programma- ble factors. The operation is done by STA015 em- beddedsoftware and it is transparent to the user. The STA015 PLL can drive directly most of the com- mercial DACs families, providing an over sampling clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. 2.4 - GPSO Output Interface In order to retrieve ADPCM encoded data a Gen- eral Purpose Serial Output interface is available (in TQFP44 and LFBGA64 packages only). The maximum frequency for clock is the GPSO_SCKR DSP system clock frequency di- vided by 3 (i.e. 8.192 MHz @ 24.58MHz). The in- terface is based on a simple and configurable 3- lines protocol, as described by figure 10. STA015-STA015B-STA015T 10/44 |
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