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ST93C06CM6013TR Datasheet(PDF) 9 Page - STMicroelectronics |
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ST93C06CM6013TR Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 15 page Erase All The Erase All instruction (ERAL) erases the whole memory (all memory bits are set to ’1’). A dummy address is input during the instruction transfer and the erase is made in the same way as the ERASE instruction. If the ST93C06 is still performing the erase cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C06 will ignore any data on the bus. When the erase cycle is com- pleted, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C06 is ready to receive a new instruction. Write All For correct operation, an ERAL instruction should be executed before the WRAL instruction: the WRAL instruction DOES NOT perform an automat- ic erase before writing. The Write All instruction (WRAL) writes the Data Input byte or word to all the addresses of the memory. If the ST93C06 is still performing the write cycle, the Busy signal (Q = 0) will be returned if S is driven high, and the ST93C06 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93C06 is ready to receive a new instruction. READY/BUSY Status During every programming cycle (after a WRITE, ERASE, WRAL or ERAL instruction) the Data Out- put (Q) indicates the Ready/Busy status of the memory when the Chip Select (S) is driven High. Once the ST93C06 is Ready, the Ready/Busy status is available on the Data Output (Q) until a new start bit is decoded or the Chip Select (S) is brought Low. COMMON I/O OPERATION The Data Output (Q) and Data Input (D) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. Some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (A0) and the first data bit output by Q. The reader may also refer to the SGS-THOMSON application note ”MICROWIRE EEPROM Common I/O Opera- tion”. DIFF ERENCES BETWEEN ST93C06 AND ST93C06C Each instruction of the ST93C06 requires an Addi- tional Dummy clock pulse after the rising edge of the Chip Select input (S) and before the START bit, see Figure 9. When replacing the ST93C06 with the ST93C06C in an ap plication, it must be checked that this Dummy Clock cycle DOES NOT HAPPEN when D = 1: if it is so, this clock pulse will latch an information which is decoded by the ST93C06C as a START bit (see Figure 10) and the following bits will be decoded with a shift of one bit. AI01334 1 C S D 0 Dummy Clock pulse START Bit Figure 9. ST93C06 Timing 9/15 ST93C06, ST93C06C |
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