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ST7LITE2 Datasheet(PDF) 95 Page - STMicroelectronics |
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ST7LITE2 Datasheet(HTML) 95 Page - STMicroelectronics |
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95 / 131 page  ST7LITE2 95/131 OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables. 13.3.4.1 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 4.5 to 5.5V Notes: 1. Data based on characterization results, not tested in production 2. RCCR0 is a factory-calibrated setting for 1000kHz with ±0.2 accuracy @ TA =25°C, VDD=5V. See “INTERNAL RC OS- CILLATOR ADJUSTMENT” on page 23 3. Guaranteed by design. 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy. 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24. Symbol Parameter Conditions Min Typ Max Unit fRC Internal RC oscillator fre- quency RCCR = FF (reset value), TA=25°C,VDD=5V 760 kHz RCCR = RCCR02 ),TA=25°C,VDD=5V 1000 ACCRC Accuracy of Internal RC oscillator with RCCR=RCCR02) TA=25°C,VDD=4.5 to 5.5V -1 +1% TA=-40 to +85°C,VDD=5V -5 +2 % TA=0 to +85°C,VDD=4.5 to 5.5V -21) +21) % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=5V 9701) µA tsu(RC) RC oscillator setup time TA=25°C,VDD=5V 102) µs fPLL x8 PLL input clock 11) MHz tLOCK PLL Lock time5) 2ms tSTAB PLL Stabilization time5) 4ms ACCPLL x8 PLL Accuracy fRC = 1MHz@TA=25°C,VDD=4.5 to 5.5V 0.14) % fRC = 1MHz@TA=-40 to +85°C,VDD=5V 0.14) % tw(JIT) PLL jitter period fRC = 1MHz 83) kHz JITPLL PLL jitter ( ∆f CPU/fCPU)1 3) % IDD(PLL) PLL current consumption TA=25°C 6001) µA 1 |
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