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ST75C185CTR Datasheet(PDF) 1 Page - STMicroelectronics |
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ST75C185CTR Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 13 page  ST75C185 LOW POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS TARGET DATA ® June 2000 s MEETS STANDARD EIA-232-E s SINGLE CHIP WITH INTERFACE BETWEEN UART AND SERIAL PORT CONNECTOR s LESS THAN 20mW QUIESCENT POWER CONSUMPTION s WIDE DRIVER SUPPLY VOLTAGE: 7 TO 13.2V s DRIVER OUTPUT SLEW RATE LIMITED TO 30V/ µsMAX s RECEIVER INPUT HYSTERESIS: 1.1 TYP s PUSH-PULL RECEIVER OUTPUTS s ON CHIP RECEIVER 1 µsNOISE FILTER s FUNCTIONALLY INTERCHANGEABLE WITH STM ST75185 s ESD PROTECTION: ±10KVHUMAN BODY MODEL DESCRIPTION The ST75C185 is low power BICMOS device containing three independent drivers and five receivers that is used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device has been designed to conform to Standards ANSI/EIA-232-E. The drivers have a controlled output slew rate that is limited to a maximum of 30V/ µs and the receivers have filters that reject input noise pulses that are shorter than 1 µs. Both these features eliminate the need of external components. The ST75C185 hasn’t a power sequence fault condition. It has been designed using low-power techniques in a BICMOS tecnology. In most application the receivers contained in this device will interface to single inputs peripheral devices such as ACEs, UARTs or microprocessors. By using sampling, such peripheral devices are usuallly insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the ST75C185 receiver outputs be buffered by single gates of the HCMOS, ALS or 74F logic families. PIN CONNECTION IEC LOGIC SYMBOL AND LOGIC DIAGRAM (Micro Package) (Plastic Package) (TSSOP Package) 1/13 |
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