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ST72E121 Datasheet(PDF) 41 Page - STMicroelectronics |
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ST72E121 Datasheet(HTML) 41 Page - STMicroelectronics |
41 / 92 page 41/92 ST72E121 ST72T121 16-BIT TIMER (Cont’d) 4.3.3.5 Forced Compare In this section i may represent 1 or 2. The following bits of the CR1 register are used: When the FOLV i bit is set by software, the OLVLi bit is copied to the OCMP i pin. The OLVi bit has to be toggled in order to toggle the OCMP i pin when it is enabled (OC iE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVL i bits have no effect in both one pulse mode and PWM mode. 4.3.3.6 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corre- sponding to the length of the pulse (see the for- mula in Section 4.3.3.7). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded- icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC1-CC0 (see Table 14). Then, on a valid event on the ICAP1 pin, the coun- ter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the val- ue FFFDh is loaded in the IC1R register. When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 30). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. The ICF1 bit is set when an active edge occurs and can generate an interrupt if the ICIE bit is set. 3. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 4. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 5. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 6. When the one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. FOLV2 FOLV1 OLVL2 OLVL1 event occurs Counter = OC1R OCMP1 = OLVL1 When When on ICAP1 One pulse mode cycle OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set 41 |
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