 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ST7263 Datasheet(PDF) 80 Page - STMicroelectronics |
|
||||||||||||||||||||||||||||||
ST7263 Datasheet(HTML) 80 Page - STMicroelectronics |
|
|
80 / 109 page  ST7263 80/109 I²C BUS INTERFACE (Cont’d) I²C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event oc- curs. It is cleared by software reading SR2 register in case of error event or as described in Figure 3. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: – BTF=1 (Byte received or transmitted) – ADSL=1 (Address matched in Slave mode while ACK=1) – SB=1 (Start condition generated in Master mode) – AF=1 (No acknowledge received after byte transmission) – STOPF=1 (Stop condition detected in Slave mode) – ARLO=1 (Arbitration lost in Master mode) – BERR=1 (Bus error, misplaced Start or Stop condition detected) – Address byte successfully transmitted in Mas- ter mode. Bit 6 = Reserved. Forced to 0 by hardware. Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after de- tection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disa- bled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 = BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. This information is still updat- ed when the interface is disabled (PE=0). 0: No communication on the bus 1: Communication ongoing on the bus Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR reg- ister. It is also cleared by hardware when the inter- face is disabled (PE=0). – Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 3). BTF is cleared by reading SR1 register followed by writ- ing the next byte in DR register. – Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register con- tent or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software read- ing SR1 register or by hardware when the inter- face is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disa- bled (PE=0). 0: No Start condition 1: Start condition generated 70 EVF 0 TRA BUSY BTF ADSL M/SL SB |
Similar Part No. - ST7263 |
|
Similar Description - ST7263 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
