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ST72262G2 Datasheet(PDF) 36 Page - STMicroelectronics |
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ST72262G2 Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 171 page  ST72260G, ST72262G, ST72264G 36/171 POWER SAVING MODES (Cont’d) 8.5 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 27). The MCU can exit HALT mode on reception of ei- ther a specific interrupt (see Table 5, “Interrupt Mapping,” on page 32) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the os- cillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 26). When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” op- tion bit of the option byte. The HALT instruction when executed while the Watchdog system is en- abled, can generate a Watchdog RESET (see Section 15.1 "OPTION BYTES" on page 157 for more details). Figure 26. HALT Mode Timing Overview Figure 27. HALT Mode Flowchart Notes: 1. WDGHALT is an option bit. See option byte sec- tion for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Re- fer to Table 5, “Interrupt Mapping,” on page 32 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC reg- ister are set during the interrupt routine and cleared when the CC register is popped. HALT RUN RUN 4096 CPU CYCLE DELAY RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR HALT INSTRUCTION RESET INTERRUPT 3) Y N N Y CPU OSCILLATOR PERIPHERALS 2) I[1:0] BITS OFF OFF 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF 1 ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX 4) ON 4096 CPU CLOCK CYCLE DELAY WATCHDOG ENABLE DISABLE WDGHALT 1) 0 WATCHDOG RESET 1 |
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