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ST72262G Datasheet(PDF) 30 Page - STMicroelectronics |
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ST72262G Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 171 page  ST72260G, ST72262G, ST72264G 30/171 INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an inter- rupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 18. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. 7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in Figure 20. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0. The software priority is giv- en for each interrupt. Warning: A stack overflow may occur without no- tifying the software of the failure. Note: TLI (Top Level Interrupt) is not available in this product. Figure 19. Concurrent Interrupt Management Figure 20. Nested Interrupt Management MAIN IT4 IT2 IT1 TLI IT1 MAIN IT0 I1 SOFTWARE 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 RIM IT3 I0 10 PRIORITY LEVEL MAIN IT2 TLI MAIN IT0 3 2 1 3 3 3/0 3 11 00 01 11 11 11 RIM IT1 IT4 IT4 IT1 IT2 IT3 I1 I0 11 / 10 10 SOFTWARE PRIORITY LEVEL |
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