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ST72260G Datasheet(PDF) 54 Page - STMicroelectronics |
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ST72260G Datasheet(HTML) 54 Page - STMicroelectronics |
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54 / 171 page  ST72260G, ST72262G, ST72264G 54/171 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 11.2.2 Low Power Modes 11.2.3 Interrupts The MCC/RTC interrupt event generates an inter- rupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction). Note: The MCC/RTC interrupt wakes up the MCU from ACTIVE-HALT mode, not from HALT mode. 11.2.4 Register Description MCC CONTROL/STATUS REGISTER (MCCSR) Read /Write Reset Value: 0000 0000 (00h) Bit 7:4 = reserved Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software. A modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVE- HALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode.MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. Table 13. Main Clock Controller Register Map and Reset Values Mode Description WAIT No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode. ACTIVE- HALT No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. HALT MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from HALT” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Time base overflow event OIF OIE Yes No 1) 70 0 0 0 0 TB1 TB0 OIE OIF Counter Prescaler Time Base TB1 TB0 fOSC2 =4MHz fOSC2=8MHz 16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 1 Address (Hex.) Register Label 76 54321 0 0025h SICSR Reset Value VDS 0 VDIE 0 VDF 0 LVDRF x0 CFIE 0 CSSD 0 WDGRF x 0026h MCCSR Reset Value 0 0 0 0 TB1 0 TB0 0 OIE 0 OIF 0 |
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