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ST72101 Datasheet(PDF) 34 Page - STMicroelectronics |
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ST72101 Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 84 page  34/84 ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). The user must read the MSB first, then the LSB value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LSB of the count value at the time of the read. Whatever the timer mode used (input capture, out- put compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. This feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 4.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register. The status of the EXEDG bit determines the type of level transition on the external clock pin EXT- CLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. At least four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequen- cy must be less than a quarter of the CPU clock frequency. LSB is buffered Read MSB At t0 Read LSB Returns the buffered LSB value at t0 At t0 + ∆t Other instructions Beginning of the sequence Sequence completed 34 |
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