CAT5221YI-25 datasheet(6/16 Pages) CATALYST

Part #	CAT5221YI-25

Description	Dual Digitally Programmable Potentiometer (DPP?? with 64 Taps and I2C Interface

Download	16 Pages

Scroll/Zoom	100%

Manufacturer	CATALYST [Catalyst Semiconductor]

Direct Link	http://www.catalyst-semiconductor.com

Logo

6 / 16 page

CAT5221

Doc. No. MD-2113 Rev. K

6

Characteristics subject to change without notice

SERIAL BUS PROTOCOL

The following defines the features of the I

2C bus

protocol:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high will

be interpreted as a START or STOP condition.

The device controlling the transfer is a master,

typically a processor or controller, and the device

being controlled is the slave. The master will always

initiate data transfers and provide the clock for both

transmit and receive operations. Therefore, the

CAT5221 will be considered a slave device in all

applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT5221 monitors the

SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are

fixed as 0101 for the CAT5221 (see Figure 5). The

next four significant bits (A3, A2, A1, A0) are the

device address bits and define which device the

Master is accessing. Up to sixteen devices may be

individually addressed by the system. Typically, +5V

and ground are hard-wired to these pins to establish

the device's address.

After the Master sends a START condition and the

slave address byte, the CAT5221 monitors the bus

and responds with an acknowledge (on the SDA line)

when its address matches the transmitted slave

address.

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

Acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8

bits of data.

The CAT5221 responds with an acknowledge after

receiving a START condition and its slave address. If

the device has been selected along with a write

operation, it responds with an acknowledge after

receiving each 8-bit byte.

When the CAT5221 is in a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the

line for an acknowledge. Once it receives this

acknowledge, the CAT5221 will continue to transmit

data. If no acknowledge is sent by the Master, the

device terminates data transmission and waits for a

STOP condition.

Figure 4. Acknowledge Timing

ACKNOWLEDGE

1

START

SCL FROM

MASTER

89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Similar Part No. - CAT5221YI-25

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	CAT5221YI-25	169Kb / 16P	Dual Digitally Programmable Potentiometer with 64 Taps and I2C Interface Doc. No. MD-2113 Rev. L
	CAT5221YI-25-T2	249Kb / 16P	Dual Digitally Programmable Potentiometer (DPP?? with 64 Taps and I2C Interface Doc. No. MD-2113 Rev. M
	CAT5221YI-25-T2	211Kb / 15P	Dual Digital Potentiometer (POT) July, 2013 ??Rev. 14
Catalyst Semiconductor	CAT5221YI-25TE13	112Kb / 16P	Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface

More results

Similar Description - CAT5221YI-25

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	CAT5221	249Kb / 16P	Dual Digitally Programmable Potentiometer (DPP?? with 64 Taps and I2C Interface Doc. No. MD-2113 Rev. M
ON Semiconductor	CAT5221WI-25	169Kb / 16P	Dual Digitally Programmable Potentiometer with 64 Taps and I2C Interface Doc. No. MD-2113 Rev. L
Catalyst Semiconductor	CAT5241	301Kb / 16P	Quad Digitally Programmable Potentiometer (DPP?? with 64 Taps and I짼C Interface
ON Semiconductor	CAT5241	250Kb / 16P	Quad Digitally Programmable Potentiometer (DPP?? with 64 Taps and I짼C Interface Doc. No. MD-2011 Rev. R
Catalyst Semiconductor	CAT5132	205Kb / 14P	16 Volt Digitally Programmable Potentiometer (DPP?? with 128 Taps and I2C Interface
ON Semiconductor	CAT5132	163Kb / 14P	16 Volt Digitally Programmable Potentiometer (DPP) with 128 Taps and I2C Interface July, 2010 ??Rev. 5
ON Semiconductor	CAT5411	280Kb / 16P	Dual Digitally Programmable Potentiometers (DPP?? with 64 Taps and SPI Interface Doc. No. MD-2114 Rev. L
Catalyst Semiconductor	CAT523	236Kb / 15P	Dual Digitally Programmable Potentiometer (DPP?? with 256 Taps and Microwire Interface
ON Semiconductor	CAT523	201Kb / 15P	Dual Digitally Programmable Potentiometer (DPP?? with 256 Taps and Microwire Interface Doc. No. MD-2005 Rev. I
Catalyst Semiconductor	CAT5411_0710	275Kb / 16P	Dual Digitally Programmable Potentiometers (DPP?? with 64 Taps and SPI Interface

More results

CAT5221YI-25 Datasheet(PDF) 6 Page - Catalyst Semiconductor

CAT5221YI-25 Datasheet(HTML) 6 Page - Catalyst Semiconductor

Similar Part No. - CAT5221YI-25

Similar Description - CAT5221YI-25

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL