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CAT5132ZI-50-GT3 Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT5132ZI-50-GT3 Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 14 page CAT5132 5 Doc No. MD-2124, Rev. E © Catalyst Semiconductor, Inc. Characteristics subject to change without notice POWER UP TIMING (1)(2) l o b m y Sr e t e m a r a Pn i Mx a Ms t i n U t R U P n o i t a r e p O d a e R o t p u - r e w o P1 s m t W U P n o i t a r e p O e t i r W o t p u - r e w o P1 s m XDCP TIMING l o b m y Sr e t e m a r a Pn i Mx a Ms t i n U t O P R W e l b a t S y l p p u S r e w o P r e t f A e m i T e s n o p s e R r e p i W5 0 1s µ t L R W d e u s s I n o i t c u r t s n I r e t f A e m i T e s n o p s e R r e p i W5 0 1s µ l o b m y Sr e t e m a r a Pn i Mx a Ms t i n U t R W ) 2 . g i F e e s ( e m i T e l c y C e t i r W5 s m WRITE CYCLE LIMITS The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. RELIABILITY CHARACTERISTICS Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. l o b m y Sr e t e m a r a Pd o h t e M t s e T e c n e r e f e Rn i Mx a Ms t i n U N D N E ) 1 ( e c n a r u d n E3 3 0 1 d o h t e M t s e T , 3 8 8 - D T S - L I M0 0 0 , 0 0 1s e l c y C T R D ) 1 ( n o i t n e t e R a t a D8 0 0 1 d o h t e M t s e T , 3 8 8 - D T S - L I M0 0 1s r a e Y TYPICAL PERFORMANCE CHARACTERISTICS Resistance between RW and RL 0.000 2.000 4.000 6.000 8.000 10.000 12.000 0 163248648096 112 128 Tap position Vcc=2.7V; V+=8v Vcc=5.5V; V+=16V Icc2 (NV write) vs Temperature 0 50 100 150 200 250 300 350 400 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) Vcc = 2.7V Vcc = 5.5V |
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