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ST6215C Datasheet(PDF) 27 Page - STMicroelectronics |
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ST6215C Datasheet(HTML) 27 Page - STMicroelectronics |
27 / 105 page ![]() ST6215C/ST6225C 27/105 6 INTERRUPTS The ST6 core may be interrupted by four maska- ble interrupt sources, in addition to a Non Maska- ble Interrupt (NMI) source. The interrupt process- ing flowchart is shown in Figure 18. Maskable interrupts must be enabled by setting the GEN bit in the IOR register. However, even if they are disabled (GEN bit = 0), interrupt events are latched and may be processed as soon as the GEN bit is set. Each source is associated with a specific Interrupt Vector, located in Program space (see Interrupt Mapping table). In the vector location, the user must write a Jump instruction to the associated in- terrupt service routine. When an interrupt source generates an interrupt request, the PC register is loaded with the address of the interrupt vector, which then causes a Jump to the relevant interrupt service routine, thus serv- icing the interrupt. Interrupts are triggered by events either on exter- nal pins, or from the on-chip peripherals. Several events can be ORed on the same interrupt vector. On-chip peripherals have flag registers to deter- mine which event triggered the interrupt. 1 |