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LAN9215I Datasheet(PDF) 77 Page - SMSC Corporation |
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LAN9215I Datasheet(HTML) 77 Page - SMSC Corporation |
77 / 138 page Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support Datasheet SMSC LAN9215i 77 Revision 1.93 (12-12-07) DATASHEET 12 Reserved RO - 11 TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data FIFO underruns. R/WC 0 10 TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data FIFO is full, and another write is attempted. R/WC 0 9 TX Data FIFO Available Interrupt (TDFA). Generated when the TX data FIFO available space is greater than the programmed level. R/WC 0 8 TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status FIFO is full. R/WC 0 7 TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status FIFO reaches the programmed level. R/WC 0 6 RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued whenever a receive frame is dropped. R/WC 0 5 RX Data FIFO Level Interrupt (RDFL). Generated when the RX FIFO reaches the programmed level. R/WC 0 4 RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status FIFO is full. R/WC 0 3 RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status FIFO reaches the programmed level. R/WC 0 2-0 GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. R/WC 000 BITS DESCRIPTION TYPE DEFAULT |
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