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GS9090B Datasheet(PDF) 30 Page - Gennum Corporation

Part # GS9090B
Description  GenLINX짰 III 270Mb/s Deserializer for SDI
Download  71 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9090B Datasheet(HTML) 30 Page - Gennum Corporation

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GS9090B Data Sheet
40749 - 2
January 2007
30 of 71
3.7 DVB-ASI Functionality
The GS9090B is said to be in DVB-ASI mode once the device has detected 32
consecutive DVB-ASI words without a single word or disparity error being
generated. The device will remain in DVB-ASI mode until 32 consecutive DVB-ASI
word errors or disparity errors are detected
K28.5 sync characters in the received DVB-ASI data stream will be detected by the
device in either inverted or non-inverted form.
In Auto mode, the GS9090B sets the SMPTE_BYPASS pin LOW and the DVB_ASI
pin HIGH to indicate that it has locked to a DVB-ASI input data stream. When
operating in Manual mode, the DVB_ASI pin must be set to logic HIGH in order to
enable DVB-ASI operation. The input SMPTE_BYPASS pin will be ignored but
should not be left floating.
When using DVB-ASI mode, the use of the application circuit in Figure 3-4 is
required. The use of this application circuit will prevent the internal PLL from false
locking to a DVB-ASI signal harmonic rather than the 270MHz fundamental. This
application circuit will detect the false lock state and restart the on-chip PLL. The
application circuit does this by detecting if the LOCKED pin has been de-asserted
for longer than ~700µs, and if so resets the PLL by discharging the loop filter
capacitor through a CMOS switch.
The applications circuit below show how this can be implemented by using a
STG719 switch as a reference. Other low leakage CMOS switches may also be
substituted within the circuit.
Figure 3-4: GS9090B False Lock Restart Circuit
The circuit above can be implemented using either a small state machine in an
FPGA or general purpose I/O on a microcontroller in combination with some
firmware. Typically, a system using the GS9090B will have an existing FPGA
and/or microcontroller that may have some spare I/O that can be used to
implement the false lock restart circuit. The choice of method will depend on what
spare system resources are available. In either case, the waveform shown in
Figure 3-5 on page 31 represents how the PLL restart must be driven. The delay
values of 700µs and 20µs are nominal but the values can be longer. In the case
where the SDI inputs are not driven with a valid DVB-ASI signal, the
FPGA or
Microcontroller
GPIO
GS9090B
GS9091B
LOCKED
IN
OUT
LF+
LF-
D
S1
InS2
1
6
2
5
3
4
STG719
5
6
1
STG719
RESTART_PLL


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