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GS9090B Datasheet(PDF) 48 Page - Gennum Corporation

Part # GS9090B
Description  GenLINX짰 III 270Mb/s Deserializer for SDI
Download  71 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9090B Datasheet(HTML) 48 Page - Gennum Corporation

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GS9090B Data Sheet
40749 - 2
January 2007
48 of 71
Figure 3-8: FIFO in Video Mode
When operating in video mode, the GS9090B will write data sequentially into the
FIFO, starting with the first active pixel in location zero of the memory. In this mode,
it is possible to use the FIFO for clock phase interchange and data alignment /
delay. The extracted H, V, and F information will also be written into the FIFO. The
H, V, and F outputs will be timed to the video data read from the FIFO. (see Section
3.6.4).
The device will ensure write-side synchronization is maintained, according to the
extracted PCLK and flywheel timing information.
Full read-control of the FIFO is made available such that data will be clocked out
of the FIFO on the rising edge of the externally provided RD_CLK signal. When
there is a HIGH-to-LOW transition at the RD_RESET pin, the first pixel presented
to the video data bus will be the first 000 of the SAV (see Figure 3-9). The FIFO_LD
pulse may be used to control the RD_RESET pin.
NOTE: The RD_RESET pulse should not be held LOW for more than one RD_CLK
cycle.
Figure 3-9: RD_RESET Pulse Timing
In video mode, the ANC output signal will be timed to the data output from the FIFO
(see Section 3.9.2 for more detail).
3.10.2 DVB-ASI Mode
The internal FIFO is in DVB-ASI mode when the FIFO_EN pin is set HIGH, and the
FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to 01b. By
default, the FIFO_MODE[1:0] bits are set to 01b by the device whenever the
WR_CLK (PCLK)
H
FIFO
(Video Mode)
RD_CLK
Application Interface
10-bit Video Data
10-bit Video Data
V
F
H
V
F
ANC
ANC
WR_RESET
RD_RESET
Internal
EDH_DETECT
EDH_DETECT
000
3FF
000
XYZ
Y'CbCr DATA
RD_CLK
RD_RESET


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