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3

IRS2130D/IRS21303D/IRS2132D (J&S)PbF

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the

with all supplies biased at a 15 V differential.

Note 1:

(Please refer to the Design Tip DT97-3 for more details).

Note 2:

The CAO pin and all input pins (except CA-) are internally clamped with a 5.2 V zener diode.

Symbol

Definition

Min.

Max.

Units

IRS213(0,2)D

High side floating supply voltage

IRS21303D

High side floating offset voltage

Note 1

600

High side floating output voltage

IRS213(0,2)D

10

Low side and logic fixed supply voltage

IRS21303D

13

20

Logic ground

-5

5

Low side output voltage

0

Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP)

FAULT output voltage

Operational amplifier output voltage

Operational amplifier inverting input voltage

V

Ambient temperature

-40

125

°C

PRELIMINARY