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AD7847SQN Datasheet(PDF) 10 Page - Analog Devices |
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AD7847SQN Datasheet(HTML) 10 Page - Analog Devices |
10 / 13 page AD7837/AD7847 REV. C –10– DIGITAL INPUT CODE NA 0.6 1 4095 3584 3072 2560 2048 1536 1024 512 0.5 0.4 0.3 0.2 0.1 0.0 Figure 19. Power Variation for Circuit in Figure 9 APPLYING THE AD7837/AD7847 General Ground Management AC or transient voltages between the analog and digital grounds i.e., between AGNDA/AGNDB and DGND can cause noise injection into the analog output. The best method of ensuring that both AGNDs and DGND are equal is to connect them together at the AD7837/AD7847 on the circuit board. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AGND and DGND pins (1N914 or equivalent). Power Supply Decoupling In order to minimize noise it is recommended that the VDD and the VSS lines on the AD7837/AD7847 be decoupled to DGND using a 10 µF in parallel with a 0.1 µF ceramic capacitor. Operation with Reduced Power Supply Voltages The AD7837/AD7847 is specified for operation with VDD/VSS = ±15 V ± 5%. The part may be operated down to VDD/VSS = ± 10 V without significant linearity degradation. See typical performance graphs. The output amplifier however requires approximately 3 V of headroom so the VREF input should not approach within 3 V of either power supply voltages in order to maintain accuracy. MICROPROCESSOR INTERFACING–AD7847 Figures 20 to 22 show interfaces between the AD7847 and three popular 16-bit microprocessor systems, the 8086, MC68000 and the TMS320C10. In all interfaces, the AD7847 is memory- mapped with a separate memory address for each DAC latch. AD7847–8086 Interface Figure 20 shows an interface between the AD7847 and the 8086 microprocessor. A single MOV instruction loads the 12-bit word into the selected DAC latch and the output responds on the ris- ing edge of WR. ANALOG PANNING CIRCUIT In audio applications it is often necessary to digitally “pan” or split a single signal source into a two-channel signal while main- taining the total power delivered to both channels constant. This may be done very simply by feeding the signal into the VREF input of both DACs. The digital codes are chosen such that the code applied to DAC B is the two's complement of that applied to DAC A. In this way the signal may be panned between both channels as the digital code is changed. The total power varia- tion with this arrangement is 3 dB. For applications which require more precise power control the circuit shown in Figure 18 may be used. This circuit requires the AD7837/AD7847, an AD712 dual op amp and eight equal value resistors. Again both channels are driven with two's complementary data. The maximum power variation using this circuit is only 0.5 dBs. VOUTA VREFA VIN RLB AD7837/ AD7847 1/2 AD712 R R R R R R R R 1/2 AD712 RLA VOUTB VOUTA VOUTB VREFB Figure 18. Analog Panning Circuit The voltage output expressions for the two channels are as follows: VOUTA = –V IN NA 212 + N A VOUT B = –V IN NB 212 + N B where NA = DAC A input code in decimal (1 ≤ N A ≤ 4095) and NB = DAC B input code in decimal (1 ≤ N B ≤ 4095) with NB = 2s complement of NA. The two's complement relationship between NA and NB causes NB to increase as NA decreases and vice versa. Hence NA + NB = 4096. With NA = 2048, then NB = 2048 also; this gives the balanced condition where the power is split equally between both chan- nels. The total power variation as the signal is fully panned from Channel B to Channel A is shown in Figure 19. |
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