LM3S317 Data Sheet
May 4, 2007
3
Preliminary
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 16
About This Document..................................................................................................................... 17
Audience........................................................................................................................................................... 17
About This Manual............................................................................................................................................ 17
Related Documents .......................................................................................................................................... 17
Documentation Conventions............................................................................................................................. 17
1.
Architectural Overview ....................................................................................................... 20
1.1
Product Features ................................................................................................................................. 20
1.2
Target Applications .............................................................................................................................. 24
1.3
High-Level Block Diagram ................................................................................................................... 25
1.4
Functional Overview ............................................................................................................................ 26
1.4.1
ARM Cortex™-M3 ............................................................................................................................... 26
1.4.2
Motor Control Peripherals .................................................................................................................... 26
1.4.3
Analog Peripherals .............................................................................................................................. 27
1.4.4
Serial Communications Peripherals..................................................................................................... 27
1.4.5
System Peripherals.............................................................................................................................. 28
1.4.6
Memory Peripherals............................................................................................................................. 29
1.4.7
Additional Features.............................................................................................................................. 29
1.4.8
Hardware Details ................................................................................................................................. 30
1.5
System Block Diagram ........................................................................................................................ 31
2.
ARM Cortex-M3 Processor Core........................................................................................ 32
2.1
Block Diagram ..................................................................................................................................... 33
2.2
Functional Description ......................................................................................................................... 33
2.2.1
Serial Wire and JTAG Debug .............................................................................................................. 33
2.2.2
Embedded Trace Macrocell (ETM) ...................................................................................................... 34
2.2.3
Trace Port Interface Unit (TPIU) .......................................................................................................... 34
2.2.4
ROM Table .......................................................................................................................................... 34
2.2.5
Memory Protection Unit (MPU) ............................................................................................................ 34
2.2.6
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 34
3.
Memory Map ........................................................................................................................ 40
4.
Interrupts ............................................................................................................................. 42
5.
JTAG Interface .................................................................................................................... 45
5.1
Block Diagram ..................................................................................................................................... 46
5.2
Functional Description ......................................................................................................................... 46
5.2.1
JTAG Interface Pins............................................................................................................................. 47
5.2.2
JTAG TAP Controller ........................................................................................................................... 48
5.2.3
Shift Registers ..................................................................................................................................... 49
5.2.4
Operational Considerations ................................................................................................................. 49
5.3
Initialization and Configuration............................................................................................................. 50
5.4
Register Descriptions........................................................................................................................... 51
5.4.1
Instruction Register (IR) ....................................................................................................................... 51
5.4.2
Data Registers ..................................................................................................................................... 53
6.
System Control.................................................................................................................... 55
6.1
Functional Description ......................................................................................................................... 55
6.1.1
Device Identification............................................................................................................................. 55