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K6T2008U2A Datasheet(PDF) 8 Page - Samsung semiconductor

Part # K6T2008U2A
Description  256Kx8 bit Low Power and Low Voltage CMOS Static RAM
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K6T2008U2A Datasheet(HTML) 8 Page - Samsung semiconductor

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CMOS SRAM
K6T2008V2A, K6T2008U2A Family
Revision 2.01
October 2001
DATA RETENTION WAVE FORM
CS1 controlled
VCC
3.0/2.7V1)
2.2V
VDR
CS1
GND
Data Retention Mode
CS1
≥VCC - 0.2V
tSDR
tRDR
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high.
tWR2 is applied in case a write ends with CS2 going low.
CS2
tCW(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
tCW(2)
tWR(4)
tWP(1)
tDW
tDH
tAS(3)
tWC
CS2 controlled
VCC
3.0/2.7V1)
0.4V
VDR
CS2
GND
Data Retention Mode
tSDR
tRDR
1. 3.0V for K6T2008V2A Family, 2.7V for K6T2008U2A Family
CS2
≤0.2V


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