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LM3S2016-IRN50-A0T Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers

Part # LM3S2016-IRN50-A0T
Description  Microcontroller
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List of Figures
Figure 1-1.
Stellaris
® 2000 Series High-Level Block Diagram ............................................................... 26
Figure 2-1.
CPU Block Diagram ......................................................................................................... 34
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 35
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 44
Figure 5-2.
Test Access Port State Machine ....................................................................................... 47
Figure 5-3.
IDCODE Register Format ................................................................................................. 52
Figure 5-4.
BYPASS Register Format ................................................................................................ 53
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 53
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 55
Figure 7-1.
Flash Block Diagram ...................................................................................................... 109
Figure 8-1.
GPIO Port Block Diagram ............................................................................................... 134
Figure 8-2.
GPIODATA Write Example ............................................................................................. 135
Figure 8-3.
GPIODATA Read Example ............................................................................................. 135
Figure 9-1.
GPTM Module Block Diagram ........................................................................................ 175
Figure 9-2.
16-Bit Input Edge Count Mode Example .......................................................................... 179
Figure 9-3.
16-Bit Input Edge Time Mode Example ........................................................................... 180
Figure 9-4.
16-Bit PWM Mode Example ............................................................................................ 181
Figure 10-1.
WDT Module Block Diagram .......................................................................................... 210
Figure 11-1.
ADC Module Block Diagram ........................................................................................... 234
Figure 12-1.
UART Module Block Diagram ......................................................................................... 266
Figure 12-2.
UART Character Frame ................................................................................................. 267
Figure 12-3.
IrDA Data Modulation ..................................................................................................... 269
Figure 13-1.
SSI Module Block Diagram ............................................................................................. 306
Figure 13-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 308
Figure 13-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 309
Figure 13-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 310
Figure 13-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 310
Figure 13-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 311
Figure 13-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 312
Figure 13-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 312
Figure 13-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 313
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 314
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 315
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 315
Figure 14-1.
I2C Block Diagram ......................................................................................................... 343
Figure 14-2.
I2C Bus Configuration .................................................................................................... 344
Figure 14-3.
START and STOP Conditions ......................................................................................... 344
Figure 14-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 345
Figure 14-5.
R/S Bit in First Byte ........................................................................................................ 345
Figure 14-6.
Data Validity During Bit Transfer on the I2C Bus ............................................................... 345
Figure 14-7.
Master Single SEND ...................................................................................................... 348
Figure 14-8.
Master Single RECEIVE ................................................................................................. 349
Figure 14-9.
Master Burst SEND ....................................................................................................... 350
Figure 14-10. Master Burst RECEIVE .................................................................................................. 351
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 352
November 30, 2007
8
Preliminary
Table of Contents


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