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LTC3725EMSEPBF Datasheet(PDF) 9 Page - Linear Technology |
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LTC3725EMSEPBF Datasheet(HTML) 9 Page - Linear Technology |
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9 / 20 page  LTC3725 9 3725f Self-Starting Architecture The LTC3725 is combined with the LTC3706 to form a complete self-starting DC isolated power supply. When power is first applied, and when VCC for the LTC3725 is above the appropriate threshold, the LTC3725 begins open-loop operation using its own internal oscillator. Power is supplied to the secondary by switching the gate driver with a gradually increasing duty cycle as controlled by the rate of rise of the voltage on the SSFLT pin. A peak detector power supply for the LTC3706 allows it to begin operation even for small duty cycles. Once adequate voltage is available for the LTC3706, it provides duty cycle information and gate drive bias power using the pulse transformer as shown in Figure 1. The LTC3725 detects the appearance of this signal and transfers control of the gate drivers to the LTC3706. Simultaneously, the LTC3725 also enables the on-chip rectifier and turns off the linear regulator. Alternately, when the LTC3725 is used as a standalone primary-side controller, the gradually increasing duty cycle powers up a secondary-side reference and optoisolator and feedback is accomplished when the output of the optoisolator begins pulling down in the FB/IN+ pin. Soft-Start and Fault These two functions are implemented using the SSFLT pin. (This pin is also used for linear regulator timeout as described in the following section.) Initiating soft-start requires that: 1) the gate drive undervoltage (UVGD) goes low meaning that adequate voltage is available on the VCC pin (7.4V for the linear regulator or 13.4V for the trickle charger) and 2) the input undervoltage (UVVIN) goes low meaning that the voltage on the UVLO pin has reached the 1.242V rising threshold. During soft-start, the LTC3725 gradually charges the soft- start capacitor to ramp up the converter duty cycle. Soft- start is over when the voltage on the SSFLT pin reaches 2.8V. In normal operation, at some point before this, the LTC3725 makes a transition to controlling duty cycle using closed- loop regulation of the converter output voltage. The SSFLT pin is also used to indicate a fault. The LTC3725 recognizes faults from four origins: 1) an overcurrent fault caused by the current sense voltage on the IS pin exceed- ing the 300mV overcurrent threshold, 2) an input undervoltage fault caused by the UVLO pin falling below the 1.226V falling threshold, 3) a gate drive undervoltage fault caused by the voltage on the VCC pin falling below the 7V threshold, or 4) loss of the gate drive encoding signal from the LTC3706. Upon sensing a fault, the LTC3725 immediately turns off the gate drive and indicates a fault by quickly pulling the voltage on the SSFLT pin to within 1.3V of the voltage on the VCC pin. After indicating the fault, the LTC3725 quickly ramps down the voltage on the SSFLT pin to approxi- mately 2.8V. Then, to allow complete discharge of the secondary-side circuit, the LTC3725 slowly ramps down the voltage on the SSFLT pin to about 200mV. The LTC3725 then attempts a restart. Linear Regulator Timeout The thermal rating of the linear regulator’s external NMOS often cannot allow it to indefinitely supply bias current to the primary-side gate drives. The LTC3725 has a linear regulator timeout mechanism that also uses the SSFLT capacitor. As described in the prior section, soft-start is over once the voltage on the SSFLT pin reaches 2.8V. However, the SSFLT capacitor continues to charge and the linear regu- lator is turned off when the voltage on the SSFLT pin reaches 3.9V. The “Applications Information” section de- scribes linear regulator timeout in more detail. Volt-Second Limit The volt-second limit ensures that the power transformer core does not saturate for any combination of duty cycle and input voltage. The input of an R-C integrator is connected to VIN and its output is connected to the VSLMT pin. While the gate drive is “off,” the LTC3725 grounds the VSLMT pin. When the gate drive is turned “on” the VSLMT pin is released and the capacitor is allowed to charge in proportion to VIN. If the capacitor voltage on the VSLMT pin OPERATIO |
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