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MC13110A Datasheet(PDF) 59 Page - Motorola, Inc

Part # MC13110A
Download  68 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC13110A Datasheet(HTML) 59 Page - Motorola, Inc

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MC13110A/B MC13111A/B
PCB Board Lay–Out Considerations
The ideal printed circuit board (PCB) lay out would be
double–sided with a full ground plane on one side. The
ground plane would be divided into separate sections to
prevent any audio signal from feeding into the first local
oscillator via the ground plane. Leaded components, can
likewise, be inserted on the ground plane side to improve
shielding and isolation from the circuit side of the PCB. The
opposite side of the PCB is typically the circuit side. It has the
interconnect traces and surface mount components. In cases
where cost allows, it may be beneficial to use multi–layer
boards to further improve isolation of components and
sensitive sections (i.e. RF and audio). For the CT–0 band, it
is also permissible to use single–sided PC layouts, but with
continuous full ground fill in and around the components.
The proper placement of certain components specified in
the application circuit may be very critical. In a lay–out
design, these components should be placed before the other
less critical components are inserted. It is also imperative
that all RF paths be kept as short as possible. Finally, the
MC13110A/B and MC13111A/B ground pins should be tied to
ground at the pins and VCC pins should have adequate
decoupling to ground as close to the IC as possible. In mixed
mode systems where digital and RF/Analog circuitry are
present, the VCC and VEE buses need to be ac–decoupled
and isolated from each other. The design must also take
great caution to avoid interference with low level analog
circuits. The receiver can be particularly susceptible to
interference as they respond to signals of only a few
microvolts. Again, be sure to keep the dc supply lines for the
digital and analog portions separate. Avoid ground paths
carrying common digital and analog currents, as well.
Component Selection
The evaluation circuit schematics specify particular
components that were used to achieve the results shown in
the typical curves and tables, but alternate components
should give similar results.
The MC13110A/B and
MC13111A /B IC are capable of matching the sensitivity, IMD,
adjacent channel rejection, and other performance criteria of
a multi–chip analog cordless telephone system. For the most
part, the same external components are used as in the
multi–chip solution.
VB and PLL Vref
VB is an internally generated bandgap voltage. It functions
as an ac reference point for the operational amplifiers in the
audio section as well as for the battery detect circuitry. This
pin needs to be sufficiently filtered to reduce noise and
prevent crosstalk between Rx audio to Tx audio signal paths.
A practical capacitor range to choose that will minimize
crosstalk and noise relative to start up time is 0.5
µf to 10 µf.
The start time for a 0.5
µf capacitor is approximately 5.0 ms,
while a 10
µf capacitor is about 10 ms.
The “PLL Vref” pin is the internal supply voltage for the Rx
and Tx PLL’s. It is regulated to a nominal 2.5 V. The “VCC
Audio” pin is the supply voltage for the internal voltage
regulator. Two capacitors with 10
µF and 0.01 µF values must
be connected to the “PLL Vref” pin to filter and stabilize this
regulated voltage. The “PLL Vref” pin may be used to power
other IC’s as long as the total external load current does not
exceed 1.0 mA. The tolerance of the regulated voltage is
±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the “PLL Vref” pin is internally connected to the
“VCC Audio” pin (i.e., the power supply voltage is maintained
but is now unregulated).
It is important to note that the momentary drop in voltage
below 2.5 V during this transition may affect initial PLL lock
times and also may trigger the reset. To prevent this, the PLL
Vref capacitor described above should be kept the same or
larger than the VB capacitor, say 10
µf as shown in the
evaluation and application diagrams.
DC Coupling
Choosing the right coupling capacitors for the compander
is also critical. The coupling capacitors will have an affect on
the audio distortion, especially at lower audio frequencies. A
useful capacitor range for the compander timing capacitors is
µf to 1.0 µf. It is advised to keep the compander
capacitors the same value in both the handset and baseset
All other dc coupling capacitors in the audio section will
form high pass filters. The designer should choose the
overall cut off frequency (–3.0 dB) to be around 200 Hz.
Designing for lower cut off frequencies may add unnecessary
cost and capacitor size to the design, while selecting too high
of a cut off frequency may affect audio quality. It is not
necessary or advised to design each audio coupling
capacitors for the same cut off frequency. Design for the
overall system cut off frequency. (Note: Do not expect the
application, evaluation, nor production test schematics to
necessarily be the correct capacitor selections.) The goals of
these boards may be different than the systems approach a
designer must consider.
For the supply pins (VCC Audio and VCC RF) choose a 10
µf in parallel with a high quality 0.01 µf capacitor. Separation
of the these two supply planes is essential, too. This is to
prevent interference between the RF and audio sections. It is
always a good design practice to add additional coupling on
each supply plane to ground as well.
The IF limiter capacitors are recommended to be 0.1
Smaller values lower the gain of the limiter stage. The
–3.0 dB limiting sensitivity and SINAD may be adversely

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