SC16C850L datasheet(7/54 Pages) NXP

Part #	SC16C850L

Description	1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface

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Manufacturer	NXP [NXP Semiconductors]

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SC16C850L_4

Product data sheet

Rev. 04 — 13 December 2007

7 of 54

NXP Semiconductors

SC16C850L

1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder

D0

F4

29

I/O

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least

signiﬁcant bit and the ﬁrst data bit in a transmit or receive serial data stream.

D1

E4

30

I/O

D2

F5

31

I/O

D3

E5

32

I/O

D4

F6

1

I/O

D5

E6

3

I/O

D6

4

I/O

D7

D5

5

I/O

INT

(IRQ)

-

20

O

When 16/68 pin is at logic 1 or unconnected, this output becomes active HIGH

interrupt output. The output state is deﬁned by the user through the software

setting of MCR[5]. INT is set to the active mode when MCR[5] is set to a

logic 1. INT is set to the open-source mode when MCR[5] is set to a logic 0.

When 16/68 pin is at logic 0, this output becomes device interrupt output

(active LOW, open-drain). An external pull-up resistor to VDD is required.

INT

D1

-

O

Interrupt output (active HIGH). The output state is deﬁned by the user

through the software setting of MCR[5]. INT is set to the active mode when

MCR[5] is set to a logic 1. INT is set to the open-source mode when MCR[5] is

set to a logic 0.

IOR

(VDD)

-

14

I

When 16/68 pin is at logic 1, this input becomes the read strobe (active LOW).

When 16/68 pin is at logic 0, this input pin is not used and should be

connected to VDD.

IOR

A3

-

I

Read strobe (active LOW).

IOW

(R/W)

-

12

I

When 16/68 pin is at logic 1 or unconnected, this input becomes the write

strobe (active LOW).

When 16/68 pin is at logic 0, this input becomes read strobe when it is at logic

HIGH, and write strobe when it is at logic LOW.

IOWB4

-

I

Write strobe (active LOW).

LOWPWR

B5

9

I

Low Power. When asserted (active HIGH), the device immediately goes into

low power mode. The oscillator is shut-off and some host interface pins are

isolated from the host’s bus to reduce power consumption. The device only

returns to normal mode when the LOWPWR pin is de-asserted. On the

negative edge of a de-asserting LOWPWR signal, the device is automatically

reset and all registers return to their default reset states. This pin has an

internal pull-down resistor, therefore, it can be left unconnected (refer to

Section 6.12 “Low power feature”).

RESET

(RESET)

-23

I

Master Reset. When 16/68 pin is at logic 1 or unconnected, this input

becomes the RESET pin (active HIGH).

When 16/68 pin is at logic LOW, this input pin becomes RESET (active LOW).

(See Section 7.23 “SC16C850L external reset condition and software reset”

for initialization details.)

RESET

F1

-

I

Reset input (active HIGH). See Section 7.23 “SC16C850L external reset

condition and software reset” for initialization details.

RI

F3

27

I

Ring Indicator (active LOW). A logic 0 on this pin indicates the modem has

received a ringing signal from the telephone line. A logic 1 transition on this

input pin will generate an interrupt if modem status interrupt is enabled. Status

can be tested by reading MCR[6].

Table 2.

Pin description …continued

Symbol

Type

Description

TFBGA36

HVQFN32

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