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Active Modes

Acquire Mode (PLL approaches lock)

Transmit Mode

Parity Bit Generation

Status Detect and Operating Modes Flow diagram

Standby

Mode

Transmit

Mode

Acquire

Mode

TXENHigh>10 s

m

PowerUp

TXEN=0

PowerUp

TXEN=1

CLK Active

PLL AchievedLock

Shutdown

Mode

TXENLow

>10 s

m

TXENLow

>10 s

m

TXENLow

>10 s

m

PCLK

StopsorLost

PCLK

StopsorLost

PCLK

Active

PowerUp

TXEN=1

CLKInactive

SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

When TXEN is high and the PCLK input clock signal is faster than 3 MHz, the SN65LVDS301 enters Active

mode. Current consumption in Active mode depends on operating frequency and the number of data transitions

in the data payload.

The PLL is enabled and attempts to lock to the input Clock. All outputs remain in high-impedance mode. When

the PLL monitor detects stable PLL operation, the device switches from Acquire to Transmit mode. For proper

SN65LVDS301 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel

clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may

not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL

deadlock (loss of VCO oscillation).

After the PLL achieves lock, the device enters the normal transmit mode. The CLK pin outputs a copy of PCLK.

Based on the selected mode of operation, the D0, D1, and D2 outputs carry the serialized data. In 1-channel

mode, outputs D1 and D2 remain high-impedance. In the 2-channel mode, output D2 remains high-impedance.

The SN65LVDS301 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly.

The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two

reserved bits are not included in the parity generation. ODD Parity bit signaling is used. The transmitter sets the

Parity bit if the sum of the 27 data bits result in an even number of ones. The Parity bit is cleared otherwise. This

allows the receiver to verify Parity and detect single bit errors.

The SN65LVDS301 switches between the power saving and active modes in the following way:

Figure 6. Status Detect and Operating Modes Flow Diagram

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