Differential Clock Buffer/Driver
CY2SSTV850
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07457 Rev. *A
Revised December 18, 2001
STV850
Features
• Phase-locked loop clock distribution for Double Data
Rate Synchronous DRAM applications
• 1:10 differential outputs
• External Feedback pins (FBINT, FBINC) are used to syn-
chronize the outputs to the clock input
• SSCG: Spread Aware™ for EMI reduction
• 48-pin SSOP and TSSOP packages
• Conforms to JEDEC JC40 and JC42.5 DDR
specifications
Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential
clock input pair (CLKINT, CLKINC) to ten differential pair of
clock outputs (YT[0:9], YC[0:9]) and one differential pair feed-
back clock output (FBOUTT, FBOUTC). The clock outputs are
individually controlled by the serial inputs SCLK and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL
is turned off and bypassed for test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC)
and the feedback clocks (FBINT,FBINC) to provide high-per-
formance, low-skew, low-jitter output differential clocks.
Block Diagram
Pin Configuration
YT0
YC0
YT1
YC1
YT2
YC2
YT3
YC3
YT4
YC4
YT5
YC5
YT6
YC6
YT7
YC7
YT8
YC8
YT9
YC9
FBOUTT
FBOUTC
Serial
Interface
Logic
PLL
FBINT
FBINC
CLKINT
CLKINC
SDATA
SCLK
AVDD
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
YC0
YT0
VDDQ
YT1
YC1
VSS
VSS
YC2
YT2
VDD
SCLK
CLKINT
CLKINC
VDDI
AVDD
AVSS
VSS
YC3
YT3
VDDQ
YT4
YC4
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
YC5
YT5
VDDQ
YT6
YC6
VSS
VSS
YC7
YT7
VDDQ
SDATA
FBINT
FBINC
VDDQ
FBOUTC
FBOUTT
VSS
YC8
YT8
VDDQ
YT9
YC9
VSS
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