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ADSP-BF533SBBC-5V Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-BF533SBBC-5V Datasheet(HTML) 6 Page - Analog Devices |
6 / 60 page 0xFFFF FFFF 0xFFFF FFFF 0xFFE0 0000 0xFFE0 0000 The event controller on the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor handles all asynchronous and synchro nous events to the processor. The ADSP-BF531/ADSP-BF532/ ADSP-BF531/ADSP-BF532/ADSP-BF533 CORE MMR REGISTERS (2M BYTE) RESERVED SCRATCHPAD SRAM (4K BYTE) SYSTEM MMR REGISTERS (2M BYTE) RESERVED RESERVED RESERVED DATA BANK A SRAM/CACHE (16K BYTE) ASYNC MEMORY BANK 3 (1M BYTE) ASYNCMEMORY BANK2 (1M BYTE) ASYNCMEMORY BANK1 (1M BYTE) ASYNCMEMORY BANK0 (1M BYTE) SDRAM MEMORY (16M BYTE TO 128M BYTE) INSTRUCTION SRAM/CACHE (16K BYTE) RESERVED RESERVED RESERVED INSTRUCTION SRAM (16K BYTE) RESERVED RESERVED RESERVED RESERVED CORE MMR REGISTERS (2M BYTE) RESERVED SCRATCHPAD SRAM (4K BYTE) INSTRUCTION SRAM (64K BYTE) SYSTEM MMR REGISTERS (2M BYTE) RESERVED RESERVED DATA BANK B SRAM/CACHE (16K BYTE) DATA BANK B SRAM (16K BYTE) DATA BANK A SRAM/CACHE (16K BYTE) ASYNC MEMORY BANK 3 (1M BYTE) ASYNC MEMORY BANK 2 (1M BYTE) ASYNC MEMORY BANK 1 (1M BYTE) ASYNC MEMORY BANK 0 (1M BYTE) SDRAM MEMORY (16M BYTE TO 128M BYTE) INSTRUCTION SRAM/CACHE (16K BYTE) RESERVED RESERVED DATA BANK A SRAM (16K BYTE) RESERVED 0xFFC0 0000 0xFFC0 0000 0xFFB0 1000 0xFFB0 1000 0xFFB0 0000 0xFFB0 0000 0xFFA1 4000 0xFFA1 4000 0xFFA1 0000 0xFFA1 0000 0xFFA0 0000 0xFFA0 C000 0xFF90 8000 0xFFA0 8000 0xFFA0 0000 0xFF90 4000 0xFF90 8000 0xFF90 0000 0xFF90 4000 0xFF80 8000 0xFF80 8000 0xFF804000 0xFF804000 0xFF800000 0xEF00 0000 0xEF00 0000 0x2040 0000 0x20300000 0x2040 0000 0x20300000 0x2020 0000 0x2020 0000 0x2010 0000 0x2010 0000 0x2000 0000 0x2000 0000 0x0800 0000 0x0800 0000 0x0000 0000 0x0000 0000 Figure 3. ADSP-BF531 Internal/External Memory Map Figure 5. ADSP-BF533 Internal/External Memory Map Event Handling 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) RESERVED SCRATCHPAD SRAM (4K BYTE) SYSTEM MMR REGISTERS (2M BYTE) RESERVED RESERVED DATA BANK B SRAM/CACHE (16K BYTE) RESERVED DATA BANK A SRAM/CACHE (16K BYTE) ASYNC MEMORY BANK 3 (1M BYTE) ASYNC MEMORY BANK 2 (1M BYTE) ASYNC MEMORY BANK 1 (1M BYTE) ASYNC MEMORY BANK 0 (1M BYTE) SDRAM MEMORY (16M BYTE TO 128MBYTE) INSTRUCTION SRAM/CACHE (16K BYTE) RESERVED RESERVED RESERVED INSTRUCTION SRAM (32K BYTE) RESERVED 0xFFE0 0000 0xFFC0 0000 0xFFB0 1000 ADSP-BF533 processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization 0xFFB0 0000 0xFFA1 4000 ensures that servicing of a higher priority event takes prece dence over servicing of a lower priority event. The controller provides support for five different types of events: • Emulation – An emulation event causes the processor to 0xFFA1 0000 0xFFA0 8000 0xFFA0 0000 0xFF90 8000 enter emulation mode, allowing command and control of the processor via the JTAG interface. 0xFF90 4000 • Reset – This event resets the processor. • Nonmaskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI • Exceptions – Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program peripherals, as well as by an explicit software instruction. 0xFF80 8000 0xFF80 4000 0xEF00 0000 input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut down of the system. 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 flow. They are caused by input pins, timers, and other Figure 4. ADSP-BF532 Internal/External Memory Map Rev. E | Page 6 of 60 | July 2007 |
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