ADSP-BF531/ADSP-BF532/ADSP-BF533

TIMING SPECIFICATIONS

Table 12 through Table 15 describe the timing requirements for

the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor clocks.

Take care in selecting MSEL, SSEL, and CSEL ratios so as not to

exceed the maximum core clock and system clock as described

in Absolute Maximum Ratings on Page 23, and the voltage con­

trolled oscillator (VCO) operating frequencies described in

Table 14. Table 14 describes phase-locked loop operating

conditions.

Parameter

Internal Regulator Setting

T

Max

All

JUNCTION

Max

Unit

f

CCLK

CCLK Frequency (V

f

CCLK

CCLK Frequency (V

f

CCLK

CCLK Frequency (V

f

CCLK

CCLK Frequency (V

f

CCLK

CCLK Frequency (V

1.20 V

1.10 V

1.00 V

0.90 V

0.85 V

400

333

295

400

364

333

280

250

MHz

MHz

MHz

MHz

MHz

Table 13. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models

Parameter

Internal Regulator Setting

Max

Unit

f

CCLK

1

f

CCLK

2

f

CCLK

3

f

CCLK

f

CCLK

f

CCLK

f

CCLK

1.30 V

1.25 V

1.20 V

1.10 V

1.00 V

0.90 V

0.85 V

600

533

500

444

400

333

250

MHz

MHz

MHz

MHz

MHz

MHz

MHz

1 Applies to 600 MHz models only. See Ordering Guide on Page 59.

2 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 59. 533 MHz models cannot support internal regulator levels above 1.25 V.

3 Applies to 500 MHz, 533 MHz, and 600 MHz models. See Ordering Guide on Page 59. 500 MHz models cannot support internal regulator levels above 1.20 V.

Table 14. Phase-Locked Loop Operating Conditions

Parameter

Min

Max

Unit

Voltage Controlled Oscillator (VCO) Frequency

50

MHz

Table 15. System Clock (SCLK) Requirements

Parameter

1

Max

Max

Unit

MBGA/PBGA

f

SCLK

f

SCLK

LQFP

f

SCLK

f

SCLK

CLKOUT/SCLK Frequency (V

CLKOUT/SCLK Frequency (V

CLKOUT/SCLK Frequency (V

CLKOUT/SCLK Frequency (V

100

100

100

83

133

100

133

83

MHz

MHz

MHz

MHz

Rev. E

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Page 24 of 60

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July 2007