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ADSP-BF533SBB500 Datasheet(PDF) 13 Page - Analog Devices

Part # ADSP-BF533SBB500
Description  Blackfin짰 Embedded Processor
Download  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF533SBB500 Datasheet(HTML) 13 Page - Analog Devices

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ADSP-BF531/ADSP-BF532/ADSP-BF533
The power savings factor is calculated as:
power savings factor
fCCLKRED
⎛ VDDINTRED
2
tRED
= ---------------------
× -------------------------- × ⎛-----------
fCCLKNOM ⎝VDDINTNOM
⎝t
NOM
where the variables in the equation are:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
tNOM is the duration running at fCCLKNOM
tRED is the duration running at fCCLKRED
The percent power savings is calculated as:
% power savings = (1 – power savings factor) × 100%
VOLTAGE REGULATION
The Blackfin processor provides an on-chip voltage regulator
that can generate appropriate V
DDINT voltage levels from the
V
DDEXT supply. See Operating Conditions on Page 21 for regula­
tor tolerances and acceptable V
DDEXT ranges for specific models.
Figure 7 shows the typical external components required to
complete the power management system. The regulator con­
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power (V
DDEXT) supplied. While
in the hibernate state, I/O power is still being applied, eliminat­
ing the need for external buffers. The voltage regulator can be
activated from this power-down state either through an RTC
wakeup or by asserting RESET, both of which will then initiate a
boot sequence. The regulator can also be disabled and bypassed
at the user’s discretion.
SETOFDECOUPLING
2.25V TO
VDDINT
VROUT
100µF
VROUT
GND
SHORT AND LOW-
INDUCTANCE WIRE
VDDEXT
+
+
100µF
100nF
10µH
ZHCS1000
3.6V
VDDEXT
CAPACITORS
INPUT VOLTAGE
(LOW-INDUCTANCE)
RANGE
+
100µF
FDS9431A
10µF
LOW ESR
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
Figure 7. Voltage Regulator Circuit
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1-0 traces
and voltage regulator external components should be consid­
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the
ADSP-BF531/ADSP-BF532/ADSP-BF533 processors as
possible.
For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
applications note on the Analog Devices web site (www.ana­
log.com)—use site search on “EE-228”.
CLOCK SIGNALS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor can be
clocked by an external crystal, a sine wave input, or a buffered,
shaped clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci­
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor includes an on-chip oscillator circuit,
an external crystal may be used. For fundamental frequency
operation, use the circuit shown in Figure 8.
CLKOUT
CLKIN
XTAL
FOR OVERTONE
OPERATION ONLY:
18pF*
18pF*
EN
TO PLL CIRCUITRY
Blackfin
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure 8. External Crystal Connections
A parallel-resonant, fundamental frequency, microprocessor-
grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 kΩ range. Further parallel resistors are typically not rec­
ommended. The two capacitors and the series resistor shown in
Figure 8 fine tune the phase and amplitude of the sine
Rev. E
|
Page 13 of 60
|
July 2007


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