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BQ24150 Datasheet(PDF) 2 Page - Texas Instruments

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Part No. BQ24150
Description  Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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BQ24150 Datasheet(HTML) 2 Page - Texas Instruments

 
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DESCRIPTION CONTINUED
B1
C1
D1
SW
PMID
PGND
B2
C2
D2
SW
PMID
PGND
B3
C3
D3
SW
PMID
PGND
B4
C4
D4
STAT
SDA
OTG
A1
VBUS
A2
VBUS
A3
BOOT
A4
SCL
E1
CSIN
E2
AUX
PWR
E3
VREF
E4
CSOUT
bq24150
bq24151
SLUS824 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
During the charging process, the bq24150/1 monitors its junction temperature (TJ) and reduces the charge
current once TJ increases to approximately 125°C. To support USB OTG device, bq24150/1 provides VBUS
(approximately 5.05 V) by boosting the battery voltage. The bq24150/1 is available in 20-pin WCSP package.
WCSP PACKAGE
(Top View)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1
µF) to
CSOUT
E4
I
PGND if there are long inductive leads to battery.
VBUS
A1, A2
I
Charger input voltage. Bypass it with a 1-
µF ceramic capacitor from VBUS to PGND.
Connection point between reverse blocking MOSFET and high-side switching MOSFET. Bypass it
PMID
B1, B2, B3
O
with a minimum of 3.3-
µF capacitor from PMID to PGND.
SW
C1, C2, C3
O
Internal switch to output inductor connection.
Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 10-nF ceramic capacitor
BOOT
A3
O
(voltage rating above 10 V) from BOOT pin to SW pin.
PGND
D1, D2, D3
Power ground
Charge current-sense input. Battery current is sensed via the voltage drop across an external sense
CSIN
E1
I
resistor. A 0.1-
µF ceramic capacitor to PGND is required.
SCL
A4
I
I2C interface clock. Open drain output, connect a 10-k
Ω pullup resistor
SDA
B4
I/O
I2C interface data. Open drain output, connect a 10-k
Ω pullup resistor
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a
STAT
C4
O
128-
µS pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can
be used to drive a LED or communicate with a host processor.
Internal bias regulator voltage. Connect a 1-
µF ceramic capacitor from this output to PGND. External
VREF
E3
O
load on VREF is not allowed.
Auxiliary power supply, connected to the battery pack to provide power in high-impedance mode.
AUXPWR
E2
I
Bypass it with a 1-
µF ceramic capacitor from this pin to PGND.
Boost mode enable control or input current limiting selection pin. When OTG is in active status,
bq24150/1 is forced to operate in boost mode. It has higher priority over I2C control and can be
disabled through control register. The logic voltage level at OTG active status can also be controlled.
OTG
D4
I
At POR, the OTG pin is default to be used as the input current limiting selection pin. When OTG =
High, Iin – limit = 500mA and when OTG = Low, Iin – limit = 100mA, see the Control Register for
details.
2
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): bq24150 bq24151


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