2005 May 20
8 of 37
data sheet (v3)
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
SBN0064G
Avant Electronics
3.4
Signal description
Table 3
Pad signal description
To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD +0.5 V .
Pad
number
SYMBOL
I/O
DESCRIPTION
1CSM
I
Column/Segment Mapping.
This signal controls the mapping relation between the column output of the Display
Data Memory and the SBN0064G’s segment output.
If CMS=1, the mapping is called Normal Mapping. The mapping relation is that
Columns 0, 1, 2,...,62,63 of the Display Data Memory are mapped to Segments 0,
1, 2,..., 62, 63 of segment driver outputs.
If CMS=0, the mapping is called Inverted Mapping. The mapping relation is that
Columns 0, 1, 2,...,62,63 of the Display Data Memory are mapped to Segments 63,
62, 61,..., 2, 1, 0 of segment driver outputs.
2
M
Input
AC frame input.
The AC frame signal is the AC signal for generating alternating bias voltage of
reverse polarities for LCD cells.
This signal is supplied by the SBN6400G.
3VDD
Input
Power supply for logic part of the chip.
The VDD should be in the range from 2.7 volts to 5.5 volts.
4, 5, 6, 7
V3R, V2R,
V5R, V0R
Input
External LCD Bias voltage.
Note that V0R, V2R, V3R, and V5R must be connected to external bias voltages
VDD, V2, V3, and V5, respectively, and the condition VDD≥V1≥V2≥V3≥V4≥V5 must
always be met.
In addition, VLCD (VDD - V5) should not exceed 13 volts.
8VEE2
Input
Negative power supply for LCD bias.
This pad should be connected to the VEE of the external bias circuit.
9~72
SEG63~0
Output
SEGNENT driver outputs.
The output voltage level of SEGMENT outputs are decided by the combination of
the alternating frame signal (M) and display data. Depending on the value of the AC
frame signal and the display data, a single voltage level is selected from V0, V2,
V3, or V5 for SEGMENT driver, as shown in Fig. 4.
73
VEE1
Input
Negative power supply for LCD bias.
This pad should be connected to the VEE of the external bias circuit.
0
1
0
1
0
1
0
1
0
1
0
1
0
V2
V5
V3
V0
V2
V5
V3
V0
Fig.4 SEGMENT driver output voltage level
M
Display
Data bit
SEG output
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