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STK14EC8-BF15TR Datasheet(PDF) 11 Page - Simtek Corporation |
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STK14EC8-BF15TR Datasheet(HTML) 11 Page - Simtek Corporation |
11 / 19 page STK14EC8 11 Simtek Confidential Jan, 2008 Document Control #ML0060 Rev 1.1 Preliminary nvSRAM The STK14EC8 nvSRAM is made up of two func- tional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique archi- tecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14EC8 supports unlimited read and writes like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations. SRAM READ The STK14EC8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-18 determine which of the 524,288 data bytes will be accessed. When the READ is initiated by an address transition, the out- puts will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W and HSB is brought low. SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. AutoStore OPERATION The STK14EC8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). AutoStore operation is a unique feature of Simtek Quantum Trap technology that is enabled by default on the STK14EC8. During normal operation, the device will draw cur- rent from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. The voltage on the VCAP pin is driven to 3.6V by a regu- lator internal to the chip. Refer to the DC CHARAC- TERISTICS table for the size of the capacitor. A pull up should be placed on W to hold it inactive during power up. This pull-up is only effective if the W sig- nal is tri-state during power up. Many MPU’s will tri- state their controls on power up. This should be ver- ified when using the pullup. When the nvSRAM comes out on power-on-recall, the MPU must be active or the W held inactive until the MPU comes out of reset. nvSRAM OPERATION Figure 3: AutoStore Mode vCAP vCC W vCC |
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