SPT
7
3/11/97
SPT7910
TYPICAL INTERFACE CIRCUIT
The SPT7910 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7910 in
normal circuit operation. The following section provides a
description of the pin functions and outlines critical perfor-
mance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
The SPT7910 requires the use of two supply voltages, VEE
and VCC. Both supplies should be treated as analog supply
sources. This means the VEE and VCC ground returns of the
device should both be connected to the analog ground plane.
All other -5.2 V requirements of the external digital logic circuit
should be connected to the digital ground plane. Each power
supply pin should be bypassed as closely as possible to the
device with .01
µF and 10 µF capacitors as shown in
figure 2.
The two grounds available on the SPT7910 are AGND and
DGND. DGND is used only for ECL outputs and is to be
referenced to the output pulldown voltage. These grounds
are not tied together internal to the device. The use of ground
planes is recommended to achieve the best performance of
the SPT7910. The AGND and the DGND ground planes
should be separated from each other and only connected
together at the device through an inductance or ferrite bead.
Doing this will minimize the ground noise pickup.
VOLTAGE REFERENCE
The SPT7910 requires the use of two voltage references: VFT
and VFB. VFT is the force for the top of the voltage reference
ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom
of the voltage reference ladder. Both voltages are applied
across an internal reference ladder resistance of 800 ohms.
In addition, there are five reference ladder taps (VST,VRT1,
VRT2, VRT3, and VSB). VST is the sense for the top of the
reference ladder (+2.0 V), VRT2 is the midpoint of the ladder
(0.0 V typ) and VSB is the sense for the bottom of the
reference ladder (-2.0 V). VRT1 and VRT3 are quarter point
ladder taps (+1.0 and -1.0 V typical, respectively). The
voltages seen at VST and VSB are the true full scale input
voltages of the device when VFT and VFB are driven to the
recommended voltages (+2.5 V and -2.5 V typical respec-
tively). VST and VSB should be used to monitor the actual full
scale input voltage of the device. VRT1, VRT2 and VRT3
should not be driven to the expected ideal values as is
commonly done with standard flash converters. When not
being used, a decoupling capacitor of .01 uF connected to
AGND from each tap is recommended to minimize high
frequency noise injection.
Figure 2 - Typical Interface Circuit
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 (MSB)
D12 (OVERRANGE)
13 x 50
Ω
VIN2
8
VRM
.01 µF
10 µF
R
2R
2R
2R
2R
R
4
Coarse
A/D
-2 V
-5.2 V
+5 V
AGND
( 5 V RTN &
-5.2 V RTN )
DGND
( -2 V RTN )
VFT
VFB
SUCCESSIVE
INTERPOLATION
STAGE # N
SUCCESSIVE
INTERPOLATION
STAGE # i
T/H AMPLIFIER
BANK
ANALOG
PRESCALER
VIN1
+
10 µF
.01 µF
10 µF
.01 µF
+
+
L
.01 µF
1
-
2
3
4
6
7
2
VIN
VOUT
Trim
GND
R1
10 k
Ω
R2
*
30 k
Ω
R4
10 k
Ω
R3
*
30 k
Ω
IC1
IC2
(REF-03)
6
5
4
-5.2 V
.01 µF
+2.5 V
-5.2 V
+5 V
VST
.01 µF
VSB
*R2 and R3
matched to 0.1%
.01 µF
+
10 µH
+5 V
2
CLK
CLK
CLK-IN
CLK-IN
Analog
Input
Analog
Input
10 µF
+5 V
.01 µF
+
10 µF
-2.5 V
D2
D1
NOTE: D1=D2=1N5817 or equivalent. (Used to prevent damage caused by power sequencing.)
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