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ST10F280-AB Datasheet(PDF) 1 Page - STMicroelectronics

Part No. ST10F280-AB
Description  16-Bit MCU with 512K Byte FLASH and 18K Byte RAM Memories
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com

ST10F280-AB Datasheet(HTML) 1 Page - STMicroelectronics

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February 2002
This errata sheet describes the functional and electrical problems known in the revision AB of the
ST10F280-AB engineering samples.
The ST10F280-AB engineering samples marked as EAB-xxxx are not completely tested in all electrical
and functional characteristics and should be used for functional evaluation only.
Test conditions for these engineering samples are:
– TA
Room Temperature (25°C)
– Vcc
5.0V ±10%
– Fosc
40MHz, PLL disabled, direct drive (fCPU = 40MHz)
The following malfunctions are known in this step:
2.1 - PWRDN.1 - Execution of PWRDN Instruction
When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is clear in
SYSCON register) or while at least one of the port 2 pins used to exit from power-down mode (if PWRD-
CFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the
PWRDN instruction is ignored.
However, under the conditions described below, the PWRDN instruction is not ignored, and no further
instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state.
This problem only occurs in the following situations:
a) The instructions following the PWRDN instruction are located in an external memory, and a multi-
plexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is used.
b) The instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral
(XRAM,CAN), and the instructions following the PWRDN instruction are located in external memory.
In this case, the problem occurs for any bus configuration.
Note: The on-chip peripherals are still working correctly, in particular the Watchdog Timer, if not disabled,
resets the device upon an overflow. Interrupts and PEC transfers, however, cannot be processed. In case
NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered.
No problem occurs if the NMI pin is low (if PWRDCFG = 0) or if all P2 pins used to exit from power-down
mode are at inactive level (if PWRDCFG = 1): the chip normally enters powerdown mode.
Ensure that no instruction that writes to external memory or an XPeripheral preceeds the PWRDN
instruction, otherwise insert a NOP instruction in front of PWRDN. When a multiplexed bus with memory
tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM.
16-Bit MCU with 512K Byte FLASH and 18K Byte RAM Memories
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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