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DSP56301VF80 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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DSP56301VF80 Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 124 page  DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-1 Signals/Connections 1 The DSP56301 input and output signals are organized into functional groups, as shown in Table 1-1 and illustrated in Figure 1-1. The DSP56301 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 1-1. DSP56301 Functional Signal Groupings Functional Group Number of Signals by Package Type Detailed Description TQFP MAP- BGA Power (VCC) 1 25 45 Table 1-2 Ground (GND)1 26 38 Table 1-3 Clock 22 Table 1-4 PLL 33 Table 1-5 Address Bus Port A2 24 24 Table 1-6 Data Bus 24 24 Table 1-7 Bus Control 15 15 Table 1-8 Interrupt and Mode Control 5 5 Table 1-9 Host Interface (HI32) Port B3 52 52 Table 1-11 Enhanced Synchronous Serial Interface (ESSI) Ports C and D4 12 12 Table 1-12 and Table 1-13 Serial Communication Interface (SCI) Port E5 33 Table 1-14 Timer 33 Table 1-15 JTAG/OnCE Port 66 Table 1-16 Notes: 1. The number of available power and ground signals is package-dependent. In the TQFP package specific pins are dedicated internally to device subsystems. In the MAP-BGA package, power and ground connections (except those providing PLL power) connect to internal power and ground planes, respectively. 2. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. 3. Port B signals are the HI32 port signals multiplexed with the GPIO signals. 4. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. 5. Port E signals are the SCI port signals multiplexed with the GPIO signals. 6. Each device also includes several no connect (NC) pins. The number of NC connections is package-dependent: the TQFP has 9 NCs and the MAP-BGA has 20 NCs. Do not connect any line, component, trace, or via to these pins. See Chapter 3 for details. |
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