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SERC816TR Datasheet(PDF) 11 Page - STMicroelectronics |
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SERC816TR Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 23 page  11/23 SERCON816 3.5.2 Clock Input SCLK Figure 6. Timing of Clock SCLK 3.5.3 Address Latch Figure 7. Address Latch Symbol Parameter Min. Typ. Max. Unit fSCLK Clock frequency SCLK PLL used (SBAUD16=0) 32 64 MHz PLL unused (SBAUD16=1) 64 MHz tSCLK0 SCLK low 6 ns tSCLK1 SCLK high 6 ns Symbol Parameter Min. Typ. Max. Unit TALEW Pulse width ALEL, ALEH 10 ns TALESU Setup time D15-0 to falling edge ALEH, ALEL 5 ns TALEHD hold time falling edge ALEH, ALEL to D15-0 5 ns tDA Delay from D15-0 to A15-0 20 ns SCLK 1 / fSCLK tSCLK0 tSCLK1 ALEH, ALEL D15-0 A15-0 tDA tALEW tALESU tALEHD |
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