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PSD4235F2V-B-12J Datasheet(PDF) 9 Page - STMicroelectronics

Part # PSD4235F2V-B-12J
Description  Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD4235F2V-B-12J Datasheet(HTML) 9 Page - STMicroelectronics

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PSD4235G2
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo bit in PMMR0 can be
reset to 0 and the CPLD latches its outputs and
goes to Stand-by mode until the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “Power Management” on page 59 for more de-
tails.
Table 4. Methods of Programming Different Functional Blocks of the PSD
Functional Block
JTAG-ISP
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary Flash memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No


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