DS18S20-PAR

5 of 20

The master device can check the alarm flag status of all DS DS18S20-PARs on the bus by issuing an

Alarm Search [ECh] command. Any DS18S20-PARs with a set alarm flag will respond to the command,

so the master can determine exactly which DS18S20-PARs have experienced an alarm condition. If an

done to validate the alarm condition.

64-BIT LASERED ROM CODE

Each DS18S20-PAR contains a unique 64–bit code (see Figure 5) stored in ROM. The least significant 8

bits of the ROM code contain the DS18S20-PAR’s 1–wire family code: 10h. The next 48 bits contain a

unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is

calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in

the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic

allow the DS18S20-PAR to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS

SYSTEM section of this datasheet.

64-BIT LASERED ROM CODE Figure 5

8-BIT CRC

48-BIT SERIAL NUMBER

8-BIT FAMILY CODE (10h)

MEMORY

The DS18S20-PAR’s memory is organized as shown in Figure 6. The memory consists of an SRAM

purpose memory. All memory commands are described in detail in the DS18S20-PAR FUNCTION

COMMANDS section.

Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,

and 5 are reserved for internal use by the device and cannot be overwritten; these bytes will return all 1s

when read. Bytes 6 and 7 contain the COUNT REMAIN and COUNT PER ºC registers, which can be

used to calculate extended resolution results as explained in the OPERATION – MEASURING

TEMPERATURE section. Byte 8 of the scratchpad is read-only and contains the cyclic redundancy

check (CRC) code for bytes 0 through 7 of the scratchpad. The DS18S20-PAR generates this CRC using

the method described in the CRC GENERATION section.

Data is written to bytes 2 and 3 of the scratchpad using the Write Scratchpad [4Eh] command; the data

must be transmitted to the DS18S20-PAR starting with the least significant bit of byte 2. To verify data

integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is

written.

When reading the scratchpad, data is transferred over the 1-wire bus starting with the least

significant bit of byte 0.

must issue the Copy Scratchpad [48h] command.

Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM

data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM

to the scratchpad at any time using the Recall E

2

[B8h] command. The master can issue “read time slots”

(see the 1-WIRE BUS SYSTEM section) following the Recall E

indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is

done.

MSB

MSB

LSB

LSB

LSB

MSB