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CAT1321ZD2I-42GT3 Datasheet(PDF) 10 Page - Catalyst Semiconductor |
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CAT1321ZD2I-42GT3 Datasheet(HTML) 10 Page - Catalyst Semiconductor |
10 / 18 page 10 CAT1640, CAT1641 Advance Information Doc. No. MD-3012, Rev. B Figure 9. Page Write Timing *=Don’t Care Bit Figure 8. Byte Write Timing *=Don’t Care Bit Page Write The CAT1640/41 writes up to 64 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to additional 63 bytes. After each byte has been transmitted, the CAT1640/41 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten. When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1640/41 in a single write cycle. A15–A8 SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS A C K *** A15–A8 SLAVE ADDRESS S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS DATA n+63 DATA A C K S T O P A C K DATA n A C K P A C K *** |
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