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DESCRIPTION

FUNCTIONAL DIAGRAM

SN65LVCP40

Programmable

Preemphasis

Output Data

EQ

out

Input Equalization

Opens up Data Eye

Input Data After Long Backplane Trace

SN65LVCP40

SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006

DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER

•

48-Terminal QFN (Quad Flatpack)

7 mm × 7 mm × 1 mm, 0.5-mm Terminal Pitch

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Receiver Equalization and Selectable Driver

Preemphasis to Counteract High-Frequency

•

Temperature Range: -40

°C to 85°C

Transmission Line Losses

•

Integration of Two-Serial Port

•

Bidirectional Link Replicator

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Selectable Loopback

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Signal Conditioner

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Typical Power Consumption 650 mW

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XAUI 802.3ae Protocol Backplane

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30-ps Deterministic Jitter

Redundancy

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On-Chip 100-

Ω Receiver and Driver

•

Host Adapter (Applications With Internal and

Differential Termination Resistors Eliminate

External Connection to SERDES)

External Components and Reflection from

•

Signaling Rates DC to 4 Gbps Including XAUI,

Stubs

GbE, FC, HDTV

•

3.3-V Nominal Power Supply

The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and

programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy

switching, signal buffering, or performance improvements on legacy backplane hardware.

The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side

loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are

supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver

with a 2:1 input multiplexer.

The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The

receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes

deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB,

high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil

trace width.

This device operates from a single 3.3-V supply. The device has integrated 100-

Ω line termination and provides

self-biasing. The input tolerates most differential signaling levels such as LVDS, LVPECL or CML. The output

impedance matches 100-

Ω line impedance. The inputs and outputs may be ac coupled for best interconnectivity

with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the

lowest.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.