Electronic Components Datasheet Search |
|
CDCE72010RGCT Datasheet(PDF) 4 Page - Texas Instruments |
|
|
CDCE72010RGCT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 70 page CDCE72010 SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. This pin is used in CD mode only. If set to “1” or left unconnected, it disables output 9 and enables the AUXILIARY input to drive all outputs from output0 to output8 depending on the AUX_SEL 18 I EEPROM configuration. If driven low in CD mode, it enables output 9 and makes all outputs driven by the VCXO Input depending on the internal EEPROM configuration. If Auto Reference Select mode is OFF, this pin acts as an External Input Reference Select Pin; The REF_SEL signal selects one of two input clocks: REF_SEL [1]: PRI_REF is selected; REF_SEL 47 I REF_SEL [0]: SEC_REF is selected; The input has an internal 150-k Ω pullup resistor and if left unconnected it will default to logic level “1”. If Auto Reference Select mode in ON, this pin not used. This pin is active low and can be activated externally or by the corresponding bit in the SPI register (in case of logic high, the SPI setting is valid). POWER_DOWN 17 I This pin switches the device into powerdown mode The input has an internal 150-k Ω pullup resistor and if left unconnected it will default to logic level “1”. This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the default function. This pin is active low and can be activated external or via the corresponding bit in the SPI register. In the case of RESET, the CP (Charge Pump) is switched to 3-state and all counters are reset to zero. The LVPECL outputs are static low (N) and high (P) respectively, and the RESET or HOLD 33 I LVCMOS outputs are all low or high if inverted. In the case of HOLD, the CP (Charge Pump) is switched into 3-state mode only. After HOLD is released and with the next valid reference clock cycle, the charge pump is switched back into normal operation (CP stays in 3-state as long as no reference clock is valid). During HOLD, all outputs are at normal operation. This mode allows external control of “frequency hold-over” mode. The input has an internal 150-k Ω pullup resistor. VCXO IN+ 53 I VCXO input (+) for LVPECL+, LVDS+, and LVCMOS level inputs. Complementary VCXO input for LVPECL-, LVDS- inputs. In the case of a LVCMOS level VCXO IN– 52 I input on VCXO IN+, ground this pin. Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference PRI REF+ 59 I Clock. Universal input buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In PRI REF– 58 I the case of LVCMOS signaling, ground this pin. Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary SEC REF+ 62 I Reference Clock. Universal input buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. SEC REF– 61 I In the case of LVCMOS signaling, ground this pin. Analog Test Point for TI internal testing. Connect a 1k Ω pull-down resistor or leave TESTOUTA 1 A unconnected. LVCMOS output for TI internal testing. Leave unconnected unless it is configured as the STATUS 55 AO/O IREF_CP pin. In this case it should be connected to a 12-k Ω resistor to GND. CP_OUT 3 AO Charge pump output VBB 56 AO Internal voltage bias analog output LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock. This output can be programmed to be a digital lock detect or analog lock detect (see description of Analog Lock). The PLL is locked (set high), if the rising edge of either the PRI_REF or SEC_REF clock and the VCXO_IN clock at the PFD (Phase Frequency Detector) are inside PLL_LOCK 50 AI/O the lock detect window for a predefined number of successive clock cycles. The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF clock and the VCXO_IN clock at the PFD are outside the lock detect window. The lock detect window and the number of successive clock cycles are user definable (via the SPI interface). 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCE72010 |
Similar Part No. - CDCE72010RGCT |
|
Similar Description - CDCE72010RGCT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |