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TL16C752CIRHBR Datasheet(PDF) 23 Page - Texas Instruments |
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TL16C752CIRHBR Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 48 page  www.ti.com TIMING REQUIREMENTS TL16C752C DUAL UART WITH 64-BYTE FIFO SLLS646 – MARCH 2008 TA = 0°C to 70°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted) LIMITS TEST PARAMETER 1.8 V 2.5 V 3.3 V 5 V UNIT CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX tRES Reset pulse width 200 200 200 200 ns ET CP CP Clock period 63 42 32 20 ns t3w Oscillator/Clock speed 16 24 32 48 MHz t6s Address setup time 20 15 10 5 ns t6h Address hold time See Figure 15 and Figure 16 15 10 7 5 ns t7w IOR strobe width See Figure 15 and Figure 16 85 70 50 40 ns t9d Read cycle delay See Figure 16 85 70 60 50 ns t12d Delay from IOR to data See Figure 16 65 50 35 25 ns t12h Data disable time 35 25 20 15 ns t13w IOW strobe width See Figure 15 85 70 50 40 ns t15d Write cycle delay See Figure 15 85 70 60 50 ns t16s Data setup time See Figure 15 40 30 20 15 ns t16h Data hold time See Figure 15 35 25 15 10 ns t17d Delay from IOW to output 50 pF load, See Figure 17 60 40 30 20 ns Delay to set interrupt from t18d 50 pF load, See Figure 17 70 55 45 35 ns MODEM input Delay to reset interrupt from t19d 50 pF load 80 55 40 30 ns IOR t20d Delay from stop to set interrupt See Figure 18 1 1 1 1 Baudrate Delay from IOR to reset t21d 50 pF load, See Figure 18 55 45 35 25 ns interrupt t22d Delay from stop to interrupt See Figure 21 1 1 1 1 Baudrate Delay from initial IOW reset to t23d See Figure 21 8 24 8 24 8 24 8 24 Baudrate transmit star Delay from IOW to reset t24d See Figure 21 75 45 35 25 ns interrupt t25d Delay from stop to set RXRDY See Figure 19 and Figure 20 1 1 1 1 Baudrate t26d Delay from IOR to reset RXRDY See Figure 19 and Figure 20 1 1 1 1 µs t27d Delay from IOW to set TXRDY See Figure 22 and Figure 23 70 60 50 40 ns t28d Delay from start to reset TXRDY See Figure 22 and Figure 23 16 16 16 16 Baudrate Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link(s): TL16C752C |
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