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Modem Status Register (MSR)

Interrupt Enable Register (IER)

TL16C752C

DUAL UART

WITH 64-BYTE FIFO

SLLS646 – MARCH 2008

This 8-bit register provides information about the current state of the control lines from the modem, data set, or

peripheral device to the processor. It also indicates when a control input from the modem changes state.

Table 13 shows modem status register bit settings.

BIT NO.

BIT SETTINGS

0

Indicates that CTS input (or MCR[1] in loopback) has changed state. Cleared on a read.

1

Indicates that DSR input (or MCR[0] in loopback) has changed state. Cleared on a read.

2

Indicates that RI input (or MCR[2] in loopback) has changed state from low to high. Cleared on a read.

3

Indicates that CD input (or MCR[3] in loopback) has changed state. Cleared on a read.

4

This bit is equivalent to MCR[1] during local loop-back mode. It is the complement to the CTS input.

5

This bit is equivalent to MCR[0] during local loop-back mode. It is the complement to the DSR input.

6

This bit is equivalent to MCR[2] during local loop-back mode. It is the complement to the RI input.

7

This bit is equivalent to MCR[3] during local loop-back mode. It is the complement to the CD input.

(1)

The primary inputs RI, CD, CTS, DSR are all active low but their registered equivalents in the MSR and MCR (in loopback) registers are

active high.

The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR

interrupt, Xoff received, or CTS/RTS change of state from low to high. The INT output signal is activated in

response to interrupt generation. Table 14 shows interrupt enable register bit settings.

BIT NO.

BIT SETTINGS

0 = Disable the RHR interrupt

0

1 = Enable the RHR interrupt

0 = Disable the THR interrupt

1

1 = Enable the THR interrupt

0 = Disable the receiver line status interrupt

2

1 = Enable the receiver line status interrupt

0 = Disable the modem status register interrupt

3

1 = Enable the modem status register interrupt

0 = Disable sleep mode

4

1 = Enable sleep mode

0 = Disable the Xoff interrupt

5

1 = Enable the Xoff interrupt

0 = Disable the RTS interrupt

6

1 = Enable the RTS interrupt

0 = Disable the CTS interrupt

7

1 = Enable the CTS interrupt

(1)

IER[7:4] can be modified only if EFR[4] is set, i.e., EFR[4] is a write enable.

Re-enabling IER[1] causes a new interrupt, if the THR is below the threshold.

34

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