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TCA6416PWRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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TCA6416PWRG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 31 page www.ti.com DataFrom ShiftRegister WriteConfiguration Pulse WritePulse ReadPulse WritePolarityPulse Polarity Inversion Register Input Port Register Output Port Register Configuration Register V CCP GND InputPort RegisterData Polarity RegisterData ESDProtectionDiode P00toP17 OutputPort RegisterData To INT Q1 Q2 D FF C K Q Q D FF C K Q Q D FF C K Q Q D FF C K Q Q DataFrom ShiftRegister DataFrom ShiftRegister I/O Port I 2C Interface TCA6416 LOW-VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS153 – DECEMBER 2007 Simplified Schematic of P0 to P17 A. On power up or reset, all registers return to default values. When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must not be changed between the Start and the Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TCA6416 |
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