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DataFrom

ShiftRegister

WriteConfiguration

Pulse

WritePulse

ReadPulse

WritePolarityPulse

Polarity

Inversion

Register

Input

Port

Register

Output

Port

Register

Configuration

Register

V

CCP

GND

InputPort

RegisterData

Polarity

RegisterData

ESDProtectionDiode

P00toP17

OutputPort

RegisterData

To INT

Q1

Q2

D

FF

C

K

Q

Q

D

FF

C

K

Q

Q

D

FF

C

K

Q

Q

D

FF

C

K

Q

Q

DataFrom

ShiftRegister

DataFrom

ShiftRegister

I/O Port

I

TCA6416

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

SCPS153 – DECEMBER 2007

Simplified Schematic of P0 to P17

A.

On power up or reset, all registers return to default values.

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In

applied to this I/O pin should not exceed the recommended levels for proper operation.

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

the SDA input/output, while the SCL input is high (see Figure 1). After the Start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must

not be changed between the Start and the Stop conditions.

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 2).

6

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Product Folder Link(s): TCA6416