Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any

time without notice.

ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

IS64C6416

1

Rev. 00A

01/07/03

FEATURES

• High-speed access time: 15 and 20 ns

• CMOS low power operation

• TTL compatible interface levels

• Single 5V ± 10% power supply

• Fully static operation: no clock or refresh

required

• Three state outputs

• Industrial temperature available

• Available in 44-pin SOJ package and

44-pin TSOP (Type II)

DESCRIPTION

The

organized as 65,536 words by 16 bits. It is fabricated using

process coupled with innovative circuit design techniques,

yields access times as fast as 10 ns with low power consump-

tion.

When

CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down

with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs,

CE and OE. The active LOW Write

Enable (

WE) controls both writing and reading of the memory.

A data byte allows Upper Byte (

UB) and Lower Byte (LB)

access.

The IS64C6416 is packaged in the JEDEC standard 44-pin

400-mil SOJ and 44-pin TSOP (Type II).

FUNCTIONAL BLOCK DIAGRAM

ADVANCED INFORMATION

JANUARY 2003

A0-A15

CE

OE

WE

64K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB