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M9346-TRBN3T Datasheet(PDF) 27 Page - STMicroelectronics |
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M9346-TRBN3T Datasheet(HTML) 27 Page - STMicroelectronics |
27 / 27 page M93C86, M93C76, M93C66, M93C56, M93C46 DC and AC parameters 27/37 Figure 9. Synchronous timing (start and op-code input) Table 23. AC characteristics (M93Cx6-R) Test conditions specified in Table 13. and Table 11. Symbol Alt. Parameter Min.(1) 1. This product is under development. For more information, please contact your nearest ST sales office. Max.(1) Unit fC fSK Clock frequency D.C. 1 MHz tSLCH Chip Select low to Clock high 250 ns tSHCH tCSS Chip Select setup time 50 ns tSLSH (2) 2. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles. tCS Chip Select low to Chip Select high 250 ns tCHCL (3) 3. tCHCL + tCLCH ≥ 1 / fC. tSKH Clock high time 250 ns tCLCH (3) tSKL Clock low time 250 ns tDVCH tDIS Data in setup time 100 ns tCHDX tDIH Data in hold time 100 ns tCLSH tSKS Clock setup time (relative to S) 100 ns tCLSL tCSH Chip Select hold time 0 ns tSHQV tSV Chip Select to READY/BUSY status 400 ns tSLQZ tDF Chip Select low to output Hi-Z 200 ns tCHQL tPD0 Delay to output low 400 ns tCHQV tPD1 Delay to output valid 400 ns tW tWP Erase or Write cycle time 10 ms AI01428 C OP CODE OP CODE START S D OP CODE INPUT START tDVCH tSHCH tCLSH tCHCL tCLCH tCHDX |
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