PE3282A datasheet(9/14 Pages) PEREGRINE

Part #	PE3282A

Description	1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

Direct Link	http://www.peregrine-semi.com

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1.1 GHz/510 MHz Dual PLL IC

9

Peregrine Semiconductor Corporation®

Document 70/0002~07B

Table 10. foLD Programming Truth Table

X = don’t care condition

Note 1: When the foLD is disabled the output is a CMOS LOW.

Note 2: Lock detect indicates when the VCO frequency is in “lock”. When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin

will be HIGH, with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the foLD pin will be HIGH, with narrow

pulses LOW. When PLL1/PLL2 lock detect is selected the foLD pin will be HIGH with narrow pulses LOW, only when both PLL1 and PLL2

are in lock.

Note 3: The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in

close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth

acquisition upon powering up.

foLD

Output State

C14

(PLL1 fo)

C13

(PLL1 LD)

C24

(PLL2 fo)

C23

(PLL2 LD)

Disabled (Note 1)

0000

PLL1 Lock detect (Note 2) (LD1)

0100

PLL2 Lock detect (Note 2) (LD2)

0001

PLL1/PLL2 Lock detect (Note 2)

0101

PLL1 Reference divider output (fc1)

1X

00

PLL2 Reference divider output (fc2)

0X

10

PLL1 Programmable divider output (fp1)

1X

01

PLL2 Programmable divider output (fp2)

0X

11

Serial data out

1010

Reserved

1011

Reserved

1110

Counter reset (Note 3)

1111

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