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AD5544 Datasheet(PDF) 17 Page - Analog Devices |
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AD5544 Datasheet(HTML) 17 Page - Analog Devices |
17 / 20 page AD5544/AD5554 Rev. A | Page 17 of 20 If these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all input and DAC registers to either the zero-code state (MSB = 0) or the half- scale state (MSB = 1). EN SHIFT REGISTER ADDRESS DECODER A B C D TO INPUT REGISTER 19TH/17TH CLOCK SDO SDI CLK CS Figure 30. AD5544/AD5554 Equivalent Logic Interface POWER ON RESET When the VDD power supply is turned on, an internal reset strobe forces all the input and DAC registers to the zero-code state or half-scale state, depending on the MSB pin voltage. The VDD power supply should have a smooth positive ramp without drooping in order to have consistent results, especially in the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on the power-on reset performance. The DAC register data will stay at a zero or half-scale setting until a valid serial register data load takes place. ESD Protection Circuits All logic-input pins contain back-biased ESD protection Zeners connected to ground (DGND) and VDD, as shown in Figure 31. VDD DIGITAL INPUTS 5k Ω DGND Figure 31. Equivalent ESD Production Circuits Power Supply Sequence As standard practice, it is recommended to power VDD, VSS, and ground prior to any reference. The ideal power up sequence is AGNDX, DGND, VDD, VSS, VREFX, and digital inputs. A noncompli- ance power up sequence may elevate the reference current, but the devices resume normal operation once VDD and VSS are powered-up. Layout and Power Supply Bypassing It is good practice to employ a compact, minimum-lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low-ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at VDD to minimize any transient disturbance and filter any low frequency ripple (see Figure 32). Users should not apply switching regulators for VDD due to the power supply rejection ratio degradation over frequency. AGNDX VSS DGND AD5544/AD5554 VDD C3 10 µF + C1 0.1 µF C4 10 µF C2 0.1 µF VSS VDD Figure 32. Power Supply Bypassing and Grounding Connection Grounding The DGND and AGNDX pins of the AD5544/AD5554 refer as digital and analog ground references. To minimize the digital ground bounce, the DGND terminal should be joined remotely at a single point to the analog ground plane (see Figure 32). APPLICATIONS The AD5544/AD5554 are inherently 2-quadrant multiplying D/A converters. That is, they can be easily set up for unipolar output operation. The full-scale output polarity is the inverse of the reference-input voltage. In some applications it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished using an additional external ampli- fier (A2) configured as a summing amplifier (see Figure 33). In this circuit the first and second amplifiers (A1 and A2) provide a total gain of 2 which increases the output voltage span to 20 V. Biasing the external amplifier with a 10 V offset from the refer- ence voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = −10 V) to midscale (VOUT = 0 V) to full-scale (VOUT = 10 V). ( 5544 1 32768 AD For V D V REF OUT − × ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − ) (3) ( 5554 1 8192 AD For V D V REF OUT − × ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − ) (4) A2 A1 ONE CHANNEL AD5544 IOUTX RFBX VREFX VDD VSS AGNDF AGNDX VOUT 10k Ω 10k Ω 5k Ω AD588 VREF 10V DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY. –10V < VOUT < +10V Figure 33. Four-Quadrant Multiplying Application Circuit |
Similar Part No. - AD5544_04 |
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