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PSD834215JT Datasheet(PDF) 8 Page - STMicroelectronics |
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PSD834215JT Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 89 page PSD834F2V 8/89 PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 2 shows the architecture of the PSD device family. The functions of each block are de- scribed briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discus- sion can be found in the section entitled “Memory Blocks“ on page 15. The 2 Mbit (256K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equally- sized sectors that are individually selectable. The 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to Voltage Stand-by (VSTBY, PC2), data is retained in the event of power failure. Each sector of memory can be located in a differ- ent address space as defined by the user. The ac- cess times for all memory types includes the address latching and DPLD decoding time. Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or in- ternal memory and I/O. The Page Register can also be used to change the address mapping of sectors of the Flash memories into different mem- ory spaces for IAP. PLDs The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 1, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. Table 1. PLD I/O The DPLD is used to decode addresses and to generate Sector Select signals for the PSD inter- nal memory and registers. The DPLD has combi- natorial outputs. The CPLD has 16 Output Macrocells (OMC) and 3 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propaga- tion time when invoking the power management features. I/O Ports The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/O ports, PLD I/O, or latched ad- dress outputs for MCUs using multiplexed ad- dress/data buses. The JTAG pins can be enabled on Port C for In- System Programming (ISP). Ports A and B can also be configured as a data port for a non-multiplexed bus. MCU Bus Interface PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed ad- dress/data buses. The device is configured to re- spond to the MCU’s control signals, which are also used as inputs to the PLDs. For examples, please see the section entitled “MCU Bus Interface Exam- ples“ on page 39. Table 2. JTAG SIgnals on Port C JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port C. Table 2 indicates the JTAG pin assignments. Name Inputs Outputs Product Terms Decode PLD (DPLD) 73 17 42 Complex PLD (CPLD) 73 19 140 Port C Pins JTAG Signal PC0 TMS PC1 TCK PC3 TSTAT PC4 TERR PC5 TDI PC6 TDO |
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